Keithley 2601B Reference Manual page 625
2600b series system sourcemeter instrument
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Also See for 2601B:
- Quick start manual (19 pages) ,
- Instrument specifications (13 pages) ,
- Quick start manual (19 pages)
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Series 2600B System SourceMeter® Instrument Reference Manual
Bit
B0
B1
B2
B3
B4
B5-B15
As an example, to set bit B1 of the operation status SMU A trigger overrun enable register, set
status.operation.instrument.smua.trigger_overrun.enable =
status.operation.instrument.smua.trigger_overrun.ARM.
In addition to the above constants, operationRegister can be set to the numeric equivalent of the bit to set.
To set more than one bit of the register, set operationRegister to the sum of their decimal weights. For
example, to set bits B1 and B4, set operationRegister to 18 (which is the sum of 2 + 16).
Bit
Binary value
Decimal
Weights
Bit
Binary value
Decimal
Weights
Example
status.operation.instrument.smua.trigger_overrun.enable =
status.operation.instrument.smua.trigger_overrun.ARM
Also see
Operation Status Registers
status.operation.instrument.smuX.*
2600BS-901-01 Rev. B / May 2013
Value
Not used
status.operation.instrument.smuX.trigger_overrun.ARM
status.operation.instrument.smuX.trigger_overrun.SRC
status.operation.instrument.smuX.trigger_overrun.MEAS
status.operation.instrument.smuX.trigger_overrun.ENDP
Not used
B7
0/1
128
7
(2
)
B15
0/1
32,768
15
(2
)
(on page E-9)
(on page 7-282)
B6
B5
B4
0/1
0/1
0/1
64
32
16
6
5
4
(2
)
(2
)
(2
)
B14
B13
B12
0/1
0/1
0/1
16,384
8,192
4,096
14
13
12
(2
)
(2
)
(2
)
Section 7: TSP command reference
Description
Not applicable.
Set bit indicates that the
arm event detector of the
SMU was already in the
detected state when a
trigger was received.
Bit B1 decimal value: 2
Set bit indicates that the
source event detector of
the SMU was already in
the detected state when a
trigger was received.
Bit B2 decimal value: 4
Set bit indicates that the
measurement event
detector of the SMU was
already in the detected
state when a trigger was
received.
Bit B3 decimal value: 8
Set bit indicates that the
end pulse event detector of
the SMU was already in
the detected state when a
trigger was received.
Bit B4 decimal value: 16
Not applicable.
B3
B2
B1
0/1
0/1
0/1
8
4
2
3
2
1
(2
)
(2
)
(2
)
B11
B10
B9
0/1
0/1
0/1
2,048
1,024
512
11
10
9
(2
)
(2
)
(2
)
Uses a constant to sets
the ARM bit of the
operation status SMU A
trigger overrun enable
register.
B0
0/1
1
0
(2
)
B8
0/1
256
8
(2
)
7-285
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