Block Diagram - Renesas F-ZTAT H8 Series Hardware Manual

Section 11 Programmable Timing Pattern Controller
11.1.2

Block Diagram

Figure 11.1 shows a block diagram of the TPC.
ITU compare match signals
TP
15
TP
Pulse output
14
TP pins, group 3
13
TP
12
TP
11
TP
Pulse output
10
TP pins, group 2
9
TP
8
TP
7
Pulse output
TP
6
pins, group 1
TP
5
TP
4
TP
3
Pulse output
TP
2
pins, group 0
TP
1
TP
0
Legend
TPMR: TPC output mode register
TPCR: TPC output control register
NDERB: Next data enable register B
NDERA: Next data enable register A
PBDDR: Port B data direction register
PADDR: Port A data direction register
NDRB: Next data register B
NDRA: Next data register A
PBDR: Port B data register
PADR: Port A data register
Rev. 7.00 Sep 21, 2005 page 412 of 878
REJ09B0259-0700
Control logic
PBDR
PADR
Figure 11.1 TPC Block Diagram
PADDR PBDDR
NDERA NDERB
TPMR TPCR
NDRB
NDRA
Internal
data bus