Register Descriptions - Renesas F-ZTAT H8 Series Hardware Manual

Section 9 I/O Ports
9.12.2

Register Descriptions

Table 9.20 summarizes the registers of port B.
Table 9.20 Port B Registers
Address* Name
H'FFD4 Port B data direction register
H'FFD6 Port B data register
Note: * Lower 16 bits of the address.
Port B Data Direction Register (PBDDR)
PBDDR is an 8-bit write-only register that can select input or output for each pin in port B. When
pins are used for TPC output, the corresponding PBDDR bits must also be set.
Bit 7
PB DDR
7
Initial value 0
Read/Write W
While port B acts as an I/O port, a pin in port B becomes an output pin if the corresponding
PBDDR bit is set to 1, and an input pin if this bit is cleared to 0.
PBDDR is a write-only register. Its value cannot be read. All bits return 1 when read.
PBDDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode
it retains its previous setting. If a PBDDR bit is set to 1 while port B acts as an I/O port, the
corresponding pin maintains its output state in software standby mode.
Rev. 7.00 Sep 21, 2005 page 308 of 878
REJ09B0259-0700
6 5
PB DDR PB DDR PB DDR
6 5
0 0
W W
Port B data direction 7 to 0
These bits select input or output for port B pins
Abbreviation
PBDDR
PBDR
4 3 2
PB DDR PB DDR
4 3 2
0 0 0
W W W
R/W Initial Value
W H'00
R/W H'00
1 0
PB DDR PB DDR
1 0
0 0
W W