I/O Mode - Renesas F-ZTAT H8 Series Hardware Manual

Section 8 DMA Controller
8.4.2

I/O Mode

I/O mode can be selected independently for each channel.
One byte or word is transferred at each transfer request in I/O mode. A designated number of these
transfers are executed. One address is specified in the memory address register (MAR), the other
in the I/O address register (IOAR). The direction of transfer is determined automatically from the
activation source. The transfer is from the address specified in IOAR to the address specified in
MAR if activated by an SCI channel 0 receive-data-full interrupt, and from the address specified
in MAR to the address specified in IOAR otherwise.
Table 8.6 indicates the register functions in I/O mode.
Table 8.6 Register Functions in I/O Mode
Register
23
MAR
23 7
All 1s IOAR
15
ETCR
Legend
MAR: Memory address register
IOAR: I/O address register
ETCR: Execute transfer count register
MAR and IOAR specify the source and destination addresses. MAR specifies a 24-bit source or
destination address, which is incremented or decremented as each byte or word is transferred.
IOAR specifies the lower 8 bits of a fixed address. The upper 16 bits are all 1s. IOAR is not
incremented or decremented.
Rev. 7.00 Sep 21, 2005 page 220 of 878
REJ09B0259-0700
Function
Activated by
SCI 0 Receive-
Data-Full
Interrupt
Destination
0
address
register
Source
0
address
register
Transfer
0
counter
Other
Activation Initial Setting
Source Destination or
address source address
register
Destination Source or
address destination
register address
Transfer Number of
counter transfers
Operation
Incremented or
decremented
once per
transfer
Held fixed
Decremented
once per
transfer until
H'0000 is
reached and
transfer ends