Pseudo-Static Ram Refresh Control - Renesas F-ZTAT H8 Series Hardware Manual

7.3.3

Pseudo-Static RAM Refresh Control

Refresh Request Interval and Refresh Cycle Execution: The refresh request interval is
determined as in a DRAM interface, by the settings of RTCOR and bits CKS2 to CKS0 in
RTMCSR. The numbers of states required for pseudo-static RAM read/write cycles and refresh
cycles are the same as for DRAM (see table 7.4). The state transitions are as shown in figure 7.3.
Pseudo-Static RAM Control Signals: Figure 7.15 shows the control signals for pseudo-static
RAM read, write, and refresh cycles.
φ
Address
bus
CS
3
RD
HWR
LWR
RFSH
AS
Note: 16-bit access
*
Figure 7.15 Pseudo-Static RAM Control Signal Output Timing
Read cycle
Section 7 Refresh Controller
Write cycle *
Rev. 7.00 Sep 21, 2005 page 185 of 878
Refresh cycle
Area 3 top address
REJ09B0259-0700