Registers - Renesas F-ZTAT H8 Series Hardware Manual

Section 11 Programmable Timing Pattern Controller
11.1.4

Registers

Table 11.2 summarizes the TPC registers.
Table 11.2 TPC Registers
1
Address *
Name
H'FFD1 Port A data direction register
H'FFD3 Port A data register
H'FFD4 Port B data direction register
H'FFD6 Port B data register
H'FFA0 TPC output mode register
H'FFA1 TPC output control register
H'FFA2 Next data enable register B
H'FFA3 Next data enable register A
H'FFA5/ Next data register A
3
H'FFA7 *
H'FFA4 Next data register B
3
H'FFA6 *
Notes: 1. Lower 16 bits of the address.
2. Bits used for TPC output cannot be written.
3. The NDRA address is H'FFA5 when the same output trigger is selected for TPC output
groups 0 and 1 by settings in TPCR. When the output triggers are different, the NDRA
address is H'FFA7 for group 0 and H'FFA5 for group 1. Similarly, the address of NDRB
is H'FFA4 when the same output trigger is selected for TPC output groups 2 and 3 by
settings in TPCR. When the output triggers are different, the NDRB address is H'FFA6
for group 2 and H'FFA4 for group 3.
Rev. 7.00 Sep 21, 2005 page 414 of 878
REJ09B0259-0700
Abbreviation R/W
PADDR W
R/(W) *
PADR
PBDDR W
R/(W) *
PBDR
TPMR R/W
TPCR R/W
NDERB R/W
NDERA R/W
NDRA R/W
NDRB R/W
Initial Value
H'00
2
H'00
H'00
2
H'00
H'F0
H'FF
H'00
H'00
H'00
H'00