Multiprocessor Communication - Renesas F-ZTAT H8 Series Hardware Manual

• Receiving Multiprocessor Serial Data
Figure 13.12 shows a sample flowchart for receiving multiprocessor serial data and indicates
the procedure to follow.
Initialize
Start receiving
Set MPIE bit to 1 in SCR
Read ORER and FER flags in SSR
∨
FER ORER = 1
Read RDRF flag in SSR
No
RDRF = 1?
Read receive data from RDR
No
Own ID?
Read ORER and FER flags in SSR
∨
FER ORER = 1
Read RDRF flag in SSR
RDRF = 1?
Read receive data from RDR
No
Finished receiving?
Clear RE bit to 0 in SCR
End
Figure 13.12 Sample Flowchart for Receiving Multiprocessor Serial Data (1)
1
2
Yes
No
3
Yes
Yes
Yes
No
4
No
Yes
No
Error handling
Yes
(continued on next page)
Section 13 Serial Communication Interface
1. SCI initialization: the receive data function
of the RxD pin is selected automatically.
2. ID receive cycle: set the MPIE bit to 1 in SCR.
3. SCI status check and ID check: read SSR,
check that the RDRF flag is set to 1, then read
data from RDR and compare with the
processor's own ID. If the ID does not match,
set the MPIE bit to 1 again and clear the
RDRF flag to 0. If the ID matches, clear the
RDRF flag to 0.
4. SCI status check and data receiving: read
SSR, check that the RDRF flag is set to 1,
then read data from RDR.
5. Receive error handling and break detection:
if a receive error occurs, read the
ORER and FER flags in SSR to identify the error.
After executing the necessary error handling,
clear the ORER and FER flags both to 0.
Receiving cannot resume while either the ORER
or FER flag remains set to 1. When a framing
error occurs, the RxD pin can be read to detect
the break state.
5
Rev. 7.00 Sep 21, 2005 page 491 of 878
REJ09B0259-0700