Interrupt Source; Usage Notes - Renesas F-ZTAT H8 Series Hardware Manual

7.4

Interrupt Source

Compare match interrupts (CMI) can be generated when the refresh controller is used as an
interval timer. Compare match interrupt requests are masked/unmasked with the CMIE bit of
RTMCSR.
7.5

Usage Notes

When using the DRAM or pseudo-static RAM refresh function, note the following points:
• With the refresh controller, if directly connected DRAM or PSRAM is disconnected*, the
P8 /RFSH/IRQ pin and the P8
0 0
simultaneously.
Note: * When the DRAM enable bit (DRAME) or PSRAM enable bit (PSRAME) in the refresh
control register (RFSHCR) is cleared to 0 after being set to 1.
Address bus
P8 /RFSH/IRQ
0 0
P8 /CS /IRQ
1 3 1
Figure 7.23 Operation when DRAM/PSRAM Connection is Switched
• Refresh cycles are not executed while the bus is released, during software standby mode, and
when a bus cycle is greatly prolonged by insertion of wait states. When these conditions occur,
other means of refreshing are required.
• If refresh requests occur while the bus is released, the first request is held and one refresh cycle
is executed after the bus-released state ends. Figure 7.24 shows the bus cycles in this case.
/CS /IRQ pin may both become low-level outputs
1 3 1
Area 3 start address
Section 7 Refresh Controller
Rev. 7.00 Sep 21, 2005 page 195 of 878
REJ09B0259-0700