Output Timing - Renesas F-ZTAT H8 Series Hardware Manual

Section 11 Programmable Timing Pattern Controller
Sequential output of up to 16-bit patterns is possible by writing new output data to NDRA and
NDRB before the next compare match. For information on non-overlapping operation, see section
11.3.4, Non-Overlapping TPC Output.
11.3.2

Output Timing

If TPC output is enabled, NDRA/NDRB contents are transferred to PADR/PBDR and output
when the selected compare match event occurs. Figure 11.3 shows the timing of these operations
for the case of normal output in groups 2 and 3, triggered by compare match A.
φ
TCNT
GRA
Compare
match A signal
NDRB
PBDR
TP to TP
8 15
Figure 11.3 Timing of Transfer of Next Data Register Contents and Output (Example)
Rev. 7.00 Sep 21, 2005 page 428 of 878
REJ09B0259-0700
N N + 1
N
n
m
m
n
n