Register Descriptions (Full Address Mode); Memory Address Registers (Mar); I/O Address Registers (Ioar) - Renesas F-ZTAT H8 Series Hardware Manual

8.3

Register Descriptions (Full Address Mode)

In full address mode the A and B channels operate together. Full address mode is selected as
indicated in table 8.4.
8.3.1

Memory Address Registers (MAR)

A memory address register (MAR) is a 32-bit readable/writable register. MARA functions as the
source address register of the transfer, and MARB as the destination address register.
An MAR consists of four 8-bit registers designated MARR, MARE, MARH, and MARL. All bits
of MARR are reserved: they cannot be modified and are always read as 1.
Bit 31 30 29 28 27
Initial value 1 1 1 1 1
Read/Write — — — — —
MARR
The MAR value is incremented or decremented each time one byte or word is transferred,
automatically updating the source or destination memory address. For details, see section 8.3.4,
Data Transfer Control Registers (DTCR).
The MARs are not initialized by a reset or in standby mode.
8.3.2

I/O Address Registers (IOAR)

The I/O address registers (IOARs) are not used in full address mode.
26 25 24 23 22 21 20 19
1 1 1
— — — R/W R/W R/W R/W R/W
MARE
Source or destination address
18 17 16 15 14 13 12 11
Undetermined
R/W R/W R/W R/W R/W R/W R/W R/W
MARH
Rev. 7.00 Sep 21, 2005 page 209 of 878
Section 8 DMA Controller
10 9 8 7 6 5 4 3
R/W R/W R/W R/W R/W R/W R/W R/W
MARL
REJ09B0259-0700
2 1 0
R/W R/W R/W