Register Descriptions - Renesas F-ZTAT H8 Series Hardware Manual

9.9.2

Register Descriptions

Table 9.13 summarizes the registers of port 8.
Table 9.13 Port 8 Registers
Address* Name
H'FFCD Port 8 data direction
register
H'FFCF Port 8 data register
Note: * Lower 16 bits of the address.
Port 8 Data Direction Register (P8DDR)
P8DDR is an 8-bit write-only register that can select input or output for each pin in port 8.
Bits 7 to 5 are reserved. They cannot be modified and are always read as 1.
Bit
Initial value
Modes
1 to 4
Read/Write
Initial value
Modes
5 to 7
Read/Write
Modes 1 to 6 (Expanded Modes): When bits in P8DDR bit are set to 1, P8
CS
output pins. When bits in P8DDR are cleared to 0, the corresponding pins become input ports.
3
In modes 1 to 4 (expanded modes with on-chip ROM disabled), following a reset only CS
output. The other three pins are input ports. In modes 5 and 6 (expanded modes with on-chip
ROM enabled), following a reset all four pins are input ports.
When the refresh controller is enabled, P8
refresh controller is disabled, P8
setting. For details see table 9.15.
Abbreviation
P8DDR
P8DR
7 6 5
— — —
1 1 1
— — —
1 1 1
— — —
Reserved bits
is used unconditionally for RFSH output. When the
0
becomes a generic input/output port according to the P8DDR
0
R/W Mode 1 to 4
W H'F0
R/W H'E0
4 3
P8 DDR P8 DDR P8 DDR
4 3
1 0
W W
0 0
W W
Port 8 data direction 4 to 0
These bits select input or
output for port 8 pins
Rev. 7.00 Sep 21, 2005 page 285 of 878
Section 9 I/O Ports
Initial Value
Mode 5 to 7
H'E0
H'E0
2 1 0
P8 DDR P8 DDR
2 1 0
0 0 0
W W W
0 0 0
W W W
become CS
to P8
4 1
is
0
REJ09B0259-0700
to
0