Usage Notes - Renesas F-ZTAT H8 Series Hardware Manual

10.6

Usage Notes

This section describes contention and other matters requiring special attention during ITU
operations.
Contention between TCNT Write and Clear: If a counter clear signal occurs in the T
TCNT write cycle, clearing of the counter takes priority and the write is not performed. See figure
10.61.
φ
Address bus
Internal write signal
Counter clear signal
TCNT
Figure 10.61 Contention between TCNT Write and Clear
Section 10 16-Bit Integrated Timer Unit (ITU)
TCNT write cycle
T T
1 2
TCNT address
N
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T
3
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REJ09B0259-0700
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