On-chip data bus
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CPU
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Figure 10.11 Access to Timer Counter (CPU Reads TCNT, Lower Byte)
10.3.2
8-Bit Accessible Registers
The registers other than the timer counters, general registers, and buffer registers are 8-bit
registers. These registers are linked to the CPU by an internal 8-bit data bus.
Figures 10.12 and 10.13 show examples of byte read and write access to a TCR.
If a word-size data transfer instruction is executed, two byte transfers are performed.
On-chip data bus
H
CPU
L
Figure 10.12 Access to Timer Counter (CPU Writes to TCR)
Bus interface
Bus interface
Section 10 16-Bit Integrated Timer Unit (ITU)
TCNTH
TCNTL
TCR
Rev. 7.00 Sep 21, 2005 page 351 of 878
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Module
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data bus
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Module
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data bus
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