Next Data Register A (Ndra) - Renesas F-ZTAT H8 Series Hardware Manual

11.2.5

Next Data Register A (NDRA)

NDRA is an 8-bit readable/writable register that stores the next output data for TPC output groups
1 and 0 (pins TP to TP
7
TPCR occurs, NDRA contents are transferred to the corresponding bits in PADR. The address of
NDRA differs depending on whether TPC output groups 0 and 1 have the same output trigger or
different output triggers.
NDRA is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Same Trigger for TPC Output Groups 0 and 1: If TPC output groups 0 and 1 are triggered by
the same compare match event, the NDRA address is H'FFA5. The upper 4 bits belong to group 1
and the lower 4 bits to group 0. Address H'FFA7 consists entirely of reserved bits that cannot be
modified and are always read as 1.
Address H'FFA5
Bit 7
NDR7
Initial value 0
Read/Write R/W
Address H'FFA7
Bit 7
—
Initial value 1
Read/Write —
). During TPC output, when an ITU compare match event specified in
0
6 5
NDR6 NDR5
0 0
R/W R/W
Next data 7 to 4
These bits store the next output
data for TPC output group 1
6 5
— —
1 1
— —
Section 11 Programmable Timing Pattern Controller
4 3
NDR4 NDR3
0 0
R/W R/W
Next data 3 to 0
These bits store the next output
data for TPC output group 0
4 3
— —
1 1
— —
Reserved bits
Rev. 7.00 Sep 21, 2005 page 417 of 878
2 1
NDR2 NDR1 NDR0
0 0
R/W R/W R/W
2 1
— —
1 1
— —
REJ09B0259-0700
0
0
0
—
1
—