General Registers (Gra, Grb) - Renesas F-ZTAT H8 Series Hardware Manual

TCNT can be cleared to H'0000 by compare match with GRA or GRB or by input capture to GRA
or GRB (counter clearing function) in the same channel.
When TCNT overflows (changes from H'FFFF to H'0000), the OVF flag is set to 1 in TSR of the
corresponding channel.
When TCNT underflows (changes from H'0000 to H'FFFF), the OVF flag is set to 1 in TSR of the
corresponding channel.
The TCNTs are linked to the CPU by an internal 16-bit bus and can be written or read by either
word access or byte access.
Each TCNT is initialized to H'0000 by a reset and in standby mode.
10.2.8

General Registers (GRA, GRB)

The general registers are 16-bit registers. The ITU has 10 general registers, two in each channel.
Channel Abbreviation
0 GRA0, GRB0
1 GRA1, GRB1
2 GRA2, GRB2
3 GRA3, GRB3
4 GRA4, GRB4
Bit 15
Initial value 1
Read/Write R/W
A general register is a 16-bit readable/writable register that can function as either an output
compare register or an input capture register. The function is selected by settings in TIOR.
When a general register is used as an output compare register, its value is constantly compared
with the TCNT value. When the two values match (compare match), the IMFA or IMFB flag is set
to 1 in TSR. Compare match output can be selected in TIOR.
When a general register is used as an input capture register, rising edges, falling edges, or both
edges of an external input capture signal are detected and the current TCNT value is stored in the
Function
Output compare/input capture register
Output compare/input capture register; can be buffered by
buffer registers BRA and BRB
14 13 12 11 10
1 1 1 1
R/W R/W R/W R/W R/W
Section 10 16-Bit Integrated Timer Unit (ITU)
9 8 7 6
1 1 1 1 1
R/W R/W R/W R/W
Rev. 7.00 Sep 21, 2005 page 339 of 878
5 4 3 2
1 1 1 1
R/W R/W R/W R/W R/W
REJ09B0259-0700
1 0
1 1
R/W