Block Diagram - Renesas F-ZTAT H8 Series Hardware Manual

13.1.2

Block Diagram

Figure 13.1 shows a block diagram of the SCI.
RDR
RxD
RSR
TxD
SCK
Legend
RSR: Receive shift register
RDR: Receive data register
TSR: Transmit shift register
TDR: Transmit data register
SMR: Serial mode register
SCR: Serial control register
SSR: Serial status register
BRR: Bit rate register
Module data bus
TDR
TSR
Transmit/
receive control
Parity generate
Parity check
Figure 13.1 SCI Block Diagram
Section 13 Serial Communication Interface
SSR BRR
SCR
SMR
Baud rate
generator
Clock
External clock
Rev. 7.00 Sep 21, 2005 page 453 of 878
Internal
data bus
φ
φ/4
φ/16
φ/64
TEI
TXI
RXI
ERI
REJ09B0259-0700