Timer Control Registers (Tcr) - Renesas F-ZTAT H8 Series Hardware Manual

The buffer registers are linked to the CPU by an internal 16-bit bus and can be written or read by
either word or byte access.
Buffer registers are initialized to H'FFFF by a reset and in standby mode.

10.2.10 Timer Control Registers (TCR)

TCR is an 8-bit register. The ITU has five TCRs, one in each channel.
Channel Abbreviation
0 TCR0
1 TCR1
2 TCR2
3 TCR3
4 TCR4
Bit 7
—
Initial value 1
Read/Write —
Reserved bit
Each TCR is an 8-bit readable/writable register that selects the timer counter clock source, selects
the edge or edges of external clock sources, and selects how the counter is cleared.
TCR is initialized to H'80 by a reset and in standby mode.
Bit 7—Reserved: Read-only bit, always read as 1.
Function
TCR controls the timer counter. The TCRs in all channels are
functionally identical. When phase counting mode is selected in
channel 2, the settings of bits CKEG1 and CKEG0 and TPSC2
to TPSC0 in TCR2 are ignored.
6 5
CCLR1 CCLR0 CKEG1
0 0
R/W R/W R/W
Clock edge 1/0
These bits select external clock edges
Counter clear 1/0
These bits select the counter clear source
Section 10 16-Bit Integrated Timer Unit (ITU)
4 3 2
CKEG0 TPSC2
0 0 0
R/W R/W
Timer prescaler 2 to 0
These bits select the
counter clock
Rev. 7.00 Sep 21, 2005 page 341 of 878
1 0
TPSC1 TPSC0
0 0
R/W R/W
REJ09B0259-0700