Block Diagram; Pin Configuration - Renesas F-ZTAT H8 Series Hardware Manual

Section 12 Watchdog Timer
12.1.2

Block Diagram

Figure 12.1 shows a block diagram of the WDT.
Interrupt signal
(interval timer)
Reset
(internal, external)
Legend
TCNT: Timer counter
TCSR: Timer control/status register
RSTCSR: Reset control/status register
12.1.3

Pin Configuration

Table 12.1 describes the WDT output pin.
Table 12.1 WDT Pin
Name Abbreviation
RESO
Reset output
Note: * Open-drain output.
Rev. 7.00 Sep 21, 2005 page 438 of 878
REJ09B0259-0700
Overflow
Interrupt
control
RSTCSR
Reset control
Clock
Figure 12.1 WDT Block Diagram
I/O Function
Output* External output of the watchdog timer reset
signal
TCNT
TCSR
Internal clock sources
φ/2
φ/32
φ/64
φ/128
Clock
φ/256
selector
φ/512
φ/2048
φ/4096
Internal
data bus
Read/
write
control