Buffering - Renesas F-ZTAT H8 Series Hardware Manual

Section 10 16-Bit Integrated Timer Unit (ITU)
10.4.8

Buffering

Buffering operates differently depending on whether a general register is an output compare
register or an input capture register, with further differences in reset-synchronized PWM mode and
complementary PWM mode. Buffering is available only in channels 3 and 4. Buffering operations
under the conditions mentioned above are described next.
• General register used for output compare
The buffer register value is transferred to the general register at compare match.
See figure 10.46.
BR
• General register used for input capture
The TCNT value is transferred to the general register at input capture. The previous general
register value is transferred to the buffer register.
See figure 10.47.
Input capture signal
BR
Rev. 7.00 Sep 21, 2005 page 382 of 878
REJ09B0259-0700
Compare match signal
GR
Figure 10.46 Compare Match Buffering
Figure 10.47 Input Capture Buffering
Comparator
GR
TCNT
TCNT