I/O Address Registers (Ioar) - Renesas F-ZTAT H8 Series Hardware Manual

Section 8 DMA Controller
The MAR value is incremented or decremented each time one byte or word is transferred,
automatically updating the source or destination memory address. For details, see section 8.2.4,
Data Transfer Control Registers (DTCR).
The MARs are not initialized by a reset or in standby mode.
8.2.2

I/O Address Registers (IOAR)

An I/O address register (IOAR) is an 8-bit readable/writable register that specifies a source or
destination address. The IOAR value is the lower 8 bits of the address. The upper 16 address bits
are all 1 (H'FFFF).
Bit 7
Initial value
Read/Write R/W
An IOAR functions as a source or destination address register depending on how the DMAC is
activated: as a source address register if activation is by a receive-data-full interrupt from the SCI
(channel 0), and as a destination address register otherwise.
The IOAR value is held fixed. It is not incremented or decremented when a transfer is executed.
The IOARs are not initialized by a reset or in standby mode.
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6 5 4
Undetermined
R/W R/W R/W
Source or destination address
3 2
R/W R/W R/W
1 0
R/W