Interrupts; Usage Notes - Renesas F-ZTAT H8 Series Hardware Manual

Section 12 Watchdog Timer
12.4

Interrupts

During interval timer operation, an overflow generates an interval timer interrupt (WOVI). The
interval timer interrupt is requested whenever the OVF bit is set to 1 in TCSR.
12.5

Usage Notes

Contention between TCNT Write and Increment: If a timer counter clock pulse is generated
during the T state of a write cycle to TCNT, the write takes priority and the timer count is not
3
incremented. See figure 12.8.
φ
TCNT
Internal write
signal
TCNT input
clock
TCNT
Figure 12.8 Contention between TCNT Write and Increment
Changing CKS2 to CKS0 Values: Halt TCNT by clearing the TME bit to 0 in TCSR before
changing the values of bits CKS2 to CKS0.
Rev. 7.00 Sep 21, 2005 page 448 of 878
REJ09B0259-0700
Write cycle: CPU writes to TCNT
T T
1 2
N
T
3
M
Counter write data