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Technical Reference
Table 10.
I/O x APIC Interrupts
IRQ
NMI
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Notes:
1.
Default but can be changed to another IRQ.
2.
Available in APIC mode only.
3.5
PCI Conventional Interrupt Routing Map
This section describes interrupt sharing and how the interrupt signals are connected
between the PCI Conventional bus connectors and on-board PCI Conventional devices.
The PCI Conventional specification describes how interrupts can be shared between
devices attached to the PCI Conventional bus. In most cases, the small amount of
latency added by interrupt sharing does not affect the operation or throughput of the
devices. In some special cases where maximum performance is needed from a device,
a PCI Conventional device should not share an interrupt with other PCI Conventional
devices. Use the following information to avoid sharing an interrupt with a PCI
Conventional add-in card.
January 2007
Order Number: 315879-002
System Resource
I/O channel check
Reserved, interval timer
Reserved, keyboard buffer full
Reserved, cascade input from slave PIC
User available
1
COM1
User available
Diskette drive
1
LPT1
Real-time clock
User available
User available
User available
On-board mouse port (if present, else available)
Reserved, math coprocessor
Primary Serial ATA
Secondary Serial ATA
User available (through PIRQA)
User available (through PIRQB)
User available (through PIRQC)
User available (through PIRQD)
User available (through PIRQE)
User available (through PIRQF)
User available (through PIRQG)
User available (through PIRQH)
Dual-Core Intel® Xeon® Processor LV and Intel
2
2
2
2
2
2
2
2
®
3100 Chipset
User's Manual
39
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