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Intel Manuals
Computer Hardware
80286
Programmer's reference manual
Intel 80286 Programmer's Reference Manual
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Contents
Table of Contents
Bookmarks
Table of Contents
Table of Contents
Implied Segment Usage by Index, Pointer, and Base Registers
Segment Register Selection Rules
Status Flags' Functions
Control Flags' Functions
Interpretation of Conditional Transfers
Interrupt Processing Order
Dedicated and Reserved Interrupt Vectors in Real Address Mode
Processor State after RESET
Addressing Segments of a Module Within a Task
Descriptor Cache Registers
Code and Data Segments Assigned to a Privilege Level
Selector Fields
Segment Access Rights Byte Format
Access Byte Examples
Allowed Segment Types in Segment Registers
Pointer Privilege Stamping
Gate Descriptor Format
Call Gate Checks
Call Gate
Stack Contents after an Inter-Level Call
Inter-Level Return Checks
Task State Segment and TSS Registers
TSS Descriptor
Checks Made During a Task Switch
Effect of a Task Switch on BUSY and NT Bits and the Link Word
Task Gate Descriptor
Task Switch through a Task Gate
Interrupt Descriptor Table Definition
Trap/Interrupt Gate Descriptors
Stack Layout after an Exception with an Error Code
Trap and Interrupt Gate Checks
Interrupt and Gate Interactions
Interrupt Descriptor Table Definition
Data Type for Global Descriptor Table and Interrupt Descriptor Table
Expand-Down Segment
Dynamic Segment Relocation and Expansion of Segment Limit
Example of NPX Context Switching
Table Title Page
Comparison Instructions
Transcendental Instructions
Constant Instructions
Processor Control Instructions
Instruction Set Reference Information
Instruction Execution Time
Bus Transfers
Instruction Length
Programming Facilities
High-Level Languages
Asm286
Defining Data
Records and Structures
Addressing Modes
80287 Emulation
Concurrent Processing with the 80287
Managing Concurrency
Instruction Synchronization
Data Synchronization
Error Synchronization
Incorrect Error Synchronization
Proper Error Synchronization
System-Level Numeric Programming
80287 Architecture
Processor Extension Data Channel
Real-Address Mode and Protected Virtual-Address Mode
Dedicated and Reserved I/O Locations
Processor Initialization and Control
System Initialization
Recognizing the 80287 NPX
Configuring the Numerics Environment
Initializing the 80287
80287 Emulation
Handling Numeric Processing Exceptions
Simultaneous Exception Response
Exception Recovery Examples
Conditional Branching Examples
Exception Handling Examples
Floating-Point to ASCII Conversion Examples
Function Partitioning
Exception Considerations
Special Instructions
Description of Operation
Scaling the Value
In Scaling
Avoiding Underflow and Overflow
Final Adjustments
Output Format
Trigonometric Calculation Examples
FPTAN and FPREM
Cosine Uses Sine Code
Machine Instruction Encoding and Decoding
Compatibility between the 80287 Npx and the 8087
Implementing the Ieee P754 Standard
Options Implemented in the 80287
Areas of the Standard Implemented in Software
Additional Software to Meet the Standard
Glossary of 80287 and Floating-Point Terminology
Index
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Table of Contents
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Implied Segment Usage by Index, Pointer, and Base Registers
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Status Flags' Functions
4
Processor State after Reset
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Summary of Contents for Intel 80286
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Page 40: Implied Segment Usage By Index, Pointer, And Base Registers
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Page 45: Segment Register Selection Rules
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Page 62: Status Flags' Functions
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Page 76: Interpretation Of Conditional Transfers
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Page 104: Interrupt Processing Order
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Page 180: Interrupt Descriptor Table Definition
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Page 350: Table Title Page
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Page 402: Comparison Instructions
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Page 413: Instruction Set Reference Information
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Page 430: Programming Facilities
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Page 437: 80287 Emulation
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Page 440: Managing Concurrency
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Page 441: Data Synchronization
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Page 442: Error Synchronization
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Page 443
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Page 444: Incorrect Error Synchronization
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Page 445: System-Level Numeric Programming
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Page 446
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Page 447: 80287 Architecture
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Page 448: Dedicated And Reserved I/O Locations
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Page 449
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Page 450: Configuring The Numerics Environment
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Page 451: Initializing The 80287
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Page 452: Handling Numeric Processing Exceptions
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Page 453: Simultaneous Exception Response
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Page 454
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Page 455
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Page 456
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Page 457: Conditional Branching Examples
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Page 458
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Page 459: Exception Handling Examples
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Page 460
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Page 461
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Page 462
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Page 463: Floating-Point To Ascii Conversion Examples
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Page 464
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Page 465
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Page 466
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Page 467
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Page 468
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Page 469
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Page 470: Function Partitioning
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Page 471: Exception Considerations
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Page 472: Scaling The Value
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Page 473: Final Adjustments
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Page 474: Cosine Uses Sine Code
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Page 475
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Page 476
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Page 477
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Page 478
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Page 479
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Page 480
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Page 481: Machine Instruction Encoding And Decoding
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Page 482
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Page 483
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Page 484
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Page 485
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Page 486
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Page 487
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Page 488
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Page 489: Compatibility Between The 80287 Npx And The 8087
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Page 490
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Page 491
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Page 492
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Page 493: Implementing The Ieee P754 Standard
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Page 494
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Page 495: Options Implemented In The 80287
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Page 496: Additional Software To Meet The Standard
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Page 497
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Page 498
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Page 499: Glossary Of 80287 And Floating-Point Terminology
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Page 500
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Page 501
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Page 502
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Page 503
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Page 504
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Page 505
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Page 506
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Page 507: Index
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Page 508
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Page 509
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Page 510
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Page 511
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Page 512
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Page 513
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