Signal Index - Motorola MC68340 User Manual

2.1 SIGNAL INDEX

The input and output signals for the MC68340 are listed in Table 2-1. The name,
mnemonic, and brief functional description are presented. For more detail on each signal,
refer to the signal paragraph. Guaranteed timing specifications for the signals listed in
Table 2-1 can be found in Section 11 Electrical Characteristics.
Signal Name
Address Bus
Address Bus/Port A7–A0/
Interrupt Acknowledge
Data Bus
Function Codes
Chip Select 3–1/
Interrupt Request Level/
Port B4, B2, B1
Chip Select 0/Autovector
Bus Request
Bus Grant
Bus Grant Acknowledge
Data and Size
Acknowledge
Read-Modify-Write Cycle
Address Strobe
Data Strobe
Size
Read/Write
Interrupt Request Level/
Port B7, B6, B5, B3
Reset
Halt
Bus Error
System Clock
Crystal Oscillator
External Filter Capacitor
2-2
Freescale Semiconductor, Inc.
Table 2-1. Signal Index
Mnemonic
A23–A0 Lower 24 bits of the address bus
A31–A24 Upper eight bits of the address bus, parallel I/O port, or
interrupt acknowledge lines
D15–D0 The 16-bit data bus used to transfer byte or word data
FC3–FC0 Identify the processor state and the address space of the
current bus cycle
CS3–CS1
Enables peripherals at programmed addresses, interrupt
priority level to the CPU32, or parallel I/O port
CS0 Enables peripherals at programmed addresses or
requests an automatic vector
BR
Indicates that an external device requires bus mastership
BG
Indicates that current bus cycle is complete and the
MC68340 has relinquished the bus
BGACK Indicates that an external device has assumed bus
mastership
DSACK1,
Provides asynchronous data transfers and dynamic bus
DSACK0
sizing
RMC Identifies the bus cycle as part of an indivisible read -
modify-write operation
AS
Indicates that a valid address is on the address bus
DS During a read cycle, DS indicates that an external device
should place valid data on the data bus. During a write
cycle, DS indicates that valid data is on the data bus.
SIZ1, SIZ0 Indicates the number of bytes remaining to be transferred
for this cycle
R/ W
Indicates the direction of data transfer on the bus
IRQ7, IRQ6, Provides an interrupt priority level to the CPU32 or
IRQ5, IRQ3 becomes a parallel I/O port
RESET
System reset
HALT
Suspends external bus activity
BERR Indicates an invalid bus operation is being attempted
CLKOUT System clock out
EXTAL, XTAL Connections for an external crystal or oscillator to the
internal oscillator circuit
XFC Connection pin for an external capacitor to filter the circuit
of the phase-locked loop
MC68340 USER'S MANUAL
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Function
Input/
Output
Out
Out/I/O/Out
I/O
Out
Out/In/
I/O
Out/In
In
Out
In
In
Out
Out
Out
Out
Out
In/I/O
I/O
I/O
In
Out
In, Out
In
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