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I
FUNCTIONAL DESCRIPTION
in the PMMU socket.
Memory management, pari ty and the processor
clock frequency all affect the speed of the local DRAM and VMEbus
accesses.
Because the local address and data buses are used to access the on-
board DRAM, any device that uses the DRAM must become the local bus
master.
An
on-board
arbiter
handles
this
using
the
MC68~2~
arbitration logic to transfer local bus mastership from the current
master to the next.
During normal operation, the
MC68~2~
is the
local master. When the VMEbus requires use of the DRAM, the arbiter
requests, and is granted the local bus by the
MC68~2~.
At this time,
memory timing circuitry executes one DRAM cycle (read or write) and
rel inquishes the local bus mastership, after which, the
MC68~20
resumes local bus mastership.
If
a refresh cycle is required, the
current bus cycle is stretched, eliminating the need for the refresh
circuitry to obtain local bus mastership.
The user can select the address at which the on-board DRAM appears
from the VMEbus by setting S3 (an 8-position DIP switch).
This
switch is used not only to determine the address of the DRAM, but is
also used to determine the location at which the Multiprocessing
Control/Status
Register
(MPCSR)
is
located.
This mapping
is
explained in detail
in section 4.16 and mapping examples are
provided in section 3.2.4.
On-board DRAM responds to a VMEbus access only when address modifier
lines
AM~
through AMS indicate extended or standard, privileged or
non - pri vil eged data or program space.
4.9 FUNCTION CODE ASSIGNMENTS
Decoding logic on the MVME13S/136 module determines the supervisor
or user processor state and type of address space ass i gnments
controlled, for each cycle, by the collective state of the
MC68~2~
Function Code pins (FC2, FC1, and
FC~).
In addition to the standard
supervisor or user processor state and type of address space, the
MVME13S/136 modules use the CPU space assignment to implement
coprocessor, interrupt handl i ng, and other functions.
Refer to
Table 4-2 for the function code assignments.
4.10 MVHEl35/136 USE OF CPU SPACE
The MVME13S/136 devices and functional blocks respond to four types
of CPU space accesses
(FC2-FC~
=
Ill): breakpoint (MC688Sl), access
level (MC688S}), coprocessor (Me688S} and MC6888!), and interrupt
acknowledge.
The type of access determined by A19 through A}6 is
illustrated in Figure 4-3.
4-8
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