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Chapter 2
Technical Summary
The 56F805EVM is designed as a versatile hybrid controller development card for
developing real-time software and hardware products to support a new generation of
applications in digital and wireless messaging, servo and motor control, digital answering
machines, feature phones, modems, and digital cameras. The power of the 16-bit 56F805
controller, combined with the on-board 64K × 16-bit external program static RAM
(SRAM), 64K × 16-bit external data SRAM, CAN interface, Hall-Effect/Quadrature
Encoder interface, motor zero crossing logic, motor bus over-current logic, motor bus
over-voltage logic and parallel JTAG interface, makes the 56F805EVM ideal for
developing and implementing many motor controlling algorithms, as well as for learning
the architecture and instruction set of the 56F805 processor.
The main features of the 56F805EVM include:
• 56F805 16-bit +3.3V hybrid controller operating at 80MHz [U1]
• External fast static RAM (FSRAM) memory [U15], configured as:
— 64K×16-bit of program memory with 0 wait states at 70MHz
— 64K×16-bit of data memory with 0 wait states at 70MHz
• 4-Channel 10-bit Serial D/A, SPI for real-time user data display [U18]
• 8.00MHz crystal oscillator for frequency generation [Y1]
• Optional external oscillator frequency input connector [JG6 and JG18]
• Joint Test Action Group (JTAG) port interface connector for an external debug
Host Target Interface [J29]
• On-board Parallel JTAG Host Target Interface, with a connector for a PC printer
port cable [P1]
• RS-232 interface for easy connection to a host processor [U16 and P3]
• CAN interface for high speed, 1.0Mbps, communications [U20 and J26]
• CAN bypass and bus termination [J32 and JG17]
• Connector to allow the user to connect his own SPI0 / MPIO-compatible peripheral
[J16]
MOTOROLA
Freescale Semiconductor, Inc.
Technical Summary
For More Information On This Product,
Go to: www.freescale.com
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