Analog Image Processing - Canon CLC 1120 Service Manual

III. ANALOG IMAGE PROCESSING
The analog processor circuit performs the following on the output of the CCD:
Item
BGR level matching
Odd-/even-number bit integration
A/D conversion
CCD driver
PCB
G-ODD
G-EVEN
B-ODD
B-EVEN
R-ODD
R-EVEN
To CCD
COPYRIGHT © 1999 CANON INC.
The levels of the B, G, and R signals are matched to suit the B, G,
and R offset signals to correct the rate of efficiency of photo
conversion (for B, G, and R).
The image signals of the six separate channels (according to odd-
number bits and even-number bits) are held by sample hold
signals (SH), and are integrated into image signals of three
channels (B, G, R) to suit the select signal (SEL).
The A/D conversion circuit converts B, G, and R image signals
into 8-bit digital signals each in sync with the ADCLK signal, and
sends the result to the image processor PCB.
Table 4-301
Analog processor PCB
BGR level matching
Odd-/even-number
bit integration
SH
SEL
Reference pulse
generation circuit
Figure 4-301
CANON CLC1120/1130/1150 REV.0 MAR. 1999 PRINTED IN JAPAN (IMPRIME AU JAPON)
CHAPTER 4 IMAGE PROCESSING SYSTEM
Description
RGR gain, BGR offset
G
A/D
conversion
B
R
ADCLK
Image processor
PCB
8
G
8
B
8
R
HSYNC
(sync signal)
generation
circuit
4-3