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6.12 DMA Transfer End
When DMA transfer ends and the TCn bit of the DCHCn register is set to 1, a DMA transfer end interrupt
(INTDMAn) is issued to the interrupt controller (INTC) (n = 0 to 3).
6.13 Forcible Termination
In addition to the forcible interruption operation by means of NMI input, DMA transfer can be forcibly terminated by
the INITn bit of the DCHCn register (n = 0 to 3).
Remark Because the DSAn, DDAn, and DBCn registers are FIFO buffer registers, the values are held even
after a forcible termination. Also, the next transfer condition can be set even during DMA transfer. But,
because the DADCn and DCHCn registers are not buffer registers, the setting during DMA transfer is
invalid (refer to 6.9 Next Address Setting Function and 6.3.4 DMA addressing control registers 0
to 3 (DADC0 to DADC3)).
6.14 Precautions
(1) Memory boundary
The transfer operation is not guaranteed if the source or the destination address exceeds the area of DMA
objects (external memory, internal RAM, or on-chip peripheral I/O) during DMA transfer.
(2) Transfer of misaligned data
DMA transfer of 16-bit bus width misaligned data is not supported.
(3) Times related to DMA transfer
The overhead before and after DMA transfer and the minimum execution clock for DMA transfer are shown
below.
• Internal RAM access: 1 clock
Note that for external memory access, the time depends on the type of external memory connected.
(4) Bus arbitration for CPU
When an external device is targeted for DMA transfer, the CPU can access the internal ROM and internal
RAM (if they are not subject to DMA transfer).
When DMA transfer is executed between the on-chip peripheral I/O and internal RAM, the CPU can access
the internal ROM.
(5) DMA start factor
Do not start more than one DMA channel using the same start factor. If more than one DMA channel is
started, a lower priority DMA channel may be acknowledged prior to a higher priority DMA channel.
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CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER)
User's Manual U14492EJ3V0UD
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