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CHAPTER 17 SERIAL INTERFACE IIC0 ( µ PD780344Y, 780354Y SUBSERIES ONLY)
17.5.2 Addresses
The address is defined by the 7 bits of data that follow the start condition.
An address is a 7-bit data segment that is output in order to select one of the slave devices that are connected
to the master device via bus lines. Therefore, each slave device connected via the bus lines must have a unique
address.
The slave devices include hardware that detects the start condition and checks whether or not the 7-bit address
data matches the data values stored in slave address register 0 (SVA0). If the address data matches the SVA0 values,
the slave device is selected and communicates with the master device until the master device transmits a start
condition or stop condition.
SCL0
SDA0
INTIIC0
Note INTIIC0 is not issued if data other than a local address or extension code is received during slave device
operation.
The slave address and the eighth bit, which specifies the transfer direction as described in 17.5.3 Transfer
direction specification below, are together written to IIC shift register 0 (IIC0) and are then output. Received
addresses are written to IIC0.
The slave address is assigned to the higher 7 bits of IIC0.
17.5.3 Transfer direction specification
In addition to the 7-bit address data, the master device sends 1 bit that specifies the transfer direction. When this
transfer direction specification bit has a value of "0", it indicates that the master device is transmitting data to a slave
device. When the transfer direction specification bit has a value of "1", it indicates that the master device is receiving
data from a slave device.
SCL0
SDA0
INTIIC0
Note INTIIC0 is not issued if data other than a local address or extension code is received during slave device
operation.
Figure 17-10. Address
1
2
3
4
A6
A5
A4
A3
Address
Figure 17-11. Transfer Direction Specification
1
2
3
4
A6
A5
A4
A3
User's Manual U15798EJ2V0UD
5
6
7
8
9
A2
A1
A0
R/W
5
6
7
8
9
A2
A1
A0
R/W
Transfer direction specification
Note
Note
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