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CHAPTER 17 SERIAL INTERFACE IIC0 ( µ PD780344Y, 780354Y SUBSERIES ONLY)
17.5.6 Wait signal (WAIT)
The wait signal (WAIT) is used to notify the communication partner that a device (master or slave) is preparing
to transmit or receive data (i.e., is in a wait state).
Setting the SCL0 pin to low level notifies the communication partner of the wait status. When the wait status has
been canceled for both the master and slave devices, the next data transfer can begin.
(1) When master device has a nine-clock wait and slave device has an eight-clock wait
Master
IIC0
SCL0
Slave
IIC0
SCL0
ACKE0
Transfer lines
SCL0
SDA0
324
Figure 17-14. Wait Signal (1/2)
(master transmits, slave receives, and ACKE0 = 1)
Master returns to high
impedance but slave
is in wait state (low level).
6
7
8
9
Wait after output
of eighth clock
H
Wait signal
from slave
6
7
8
D2
D1
D0
User's Manual U15798EJ2V0UD
Wait after output
of ninth clock
IIC0 data write (cancel wait)
1
FFH is written to IIC0 or WREL0 is set to 1
Wait signal
from master
9
1
ACK
D7
2
3
2
3
D6
D5
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