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User's Manual
V850/SB1
32-Bit Single-Chip Microcontroller
Hardware
µ µ µ µ PD703031A
µ µ µ µ PD703031AY µ µ µ µ PD703030BY µ µ µ µ PD703034AY µ µ µ µ PD703034BY
µ µ µ µ PD703032A
µ µ µ µ PD703032AY µ µ µ µ PD703031BY µ µ µ µ PD703035AY µ µ µ µ PD703035BY
µ µ µ µ PD703033A
µ µ µ µ PD703033AY µ µ µ µ PD703032BY µ µ µ µ PD703037AY µ µ µ µ PD703036HY
µ µ µ µ PD70F3032A µ µ µ µ PD703033B
µ µ µ µ PD70F3032AY µ µ µ µ PD703033BY µ µ µ µ PD70F3035AY µ µ µ µ PD703037HY
µ µ µ µ PD70F3033A µ µ µ µ PD70F3030B µ µ µ µ PD70F3037A µ µ µ µ PD70F3035B
µ µ µ µ PD70F3033AY µ µ µ µ PD70F3030BY µ µ µ µ PD70F3037AY µ µ µ µ PD70F3035BY
Document No. U13850EJ6V0UD00 (6th edition)
Date Published February 2003 N CP(K)
Printed in Japan
TM
, V850/SB2
µ µ µ µ PD703030B
µ µ µ µ PD703031B
µ µ µ µ PD703032B
µ µ µ µ PD70F3032B
µ µ µ µ PD70F3032BY
µ µ µ µ PD70F3033B
µ µ µ µ PD70F3033BY
1999, 2000, 2003
µ µ µ µ PD703034A
µ µ µ µ PD703035A
µ µ µ µ PD703037A
µ µ µ µ PD70F3035A µ µ µ µ PD703037H
TM
µ µ µ µ PD703034B
µ µ µ µ PD703035B
µ µ µ µ PD703036H
µ µ µ µ PD70F3036H
µ µ µ µ PD70F3036HY
µ µ µ µ PD70F3037H
µ µ µ µ PD70F3037HY
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Table of Contents
Related Manuals for NEC V850/SB1
Summary of Contents for NEC V850/SB1
- Page 1 User’s Manual V850/SB1 , V850/SB2 32-Bit Single-Chip Microcontroller Hardware µ µ µ µ PD703031A µ µ µ µ PD703030B µ µ µ µ PD703034A µ µ µ µ PD703034B µ µ µ µ PD703031AY µ µ µ µ PD703030BY µ µ µ µ PD703034AY µ µ µ µ PD703034BY µ...
- Page 2 [MEMO] User’s Manual U13850EJ6V0UD...
- Page 3 C Standard Specification as defined by Philips. V850 Series, V850/SA1, V850/SB1, V850/SB2, IEBus, and Inter Equipment Bus are trademarks of NEC Electronics Corporation. Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries.
- Page 4 NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
- Page 5 Regional Information Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify: •...
- Page 6 100 Modification of description and addition of Note in 3.2.2 (2) Program status word (PSW) Addition of 3.4.5 (2) (a) V850/SB1 ( µ µ µ µ PD703031B, 703031BY), V850/SB2 ( µ µ µ µ PD703034B, 703034BY) p. 110 pp. 119, 124, 125 Modification of Note and addition of registers in 3.4.8 Peripheral I/O registers p.
- Page 7 Major Revisions in This Edition (2/3) Pages Description p. 197 Addition of 6.6 (1) While an instruction is being executed on internal ROM p. 198 Addition of 6.6 (2) While an instruction is being executed on external ROM p. 206 Addition of description in Caution in 7.1.4 (1) 16-bit timer mode control registers 0, 1 (TMC0, TMC1) p.
- Page 8 Addition of 11.7 How to Read A/D Converter Characteristics Table p. 452 Addition of 12.3 Configuration Addition of 12.4 (2) (a) V850/SB1 ( µ µ µ µ PD703031B, 703031BY), V850/SB2 ( µ µ µ µ PD703034B, 703034BY) p. 455 p. 460 Addition of Caution in 12.4 (5) DMA channel control registers 0 to 5 (DCHC0 to DCHC5)
- Page 9 INTRODUCTION Readers This manual is intended for users who wish to understand the functions of the V850/SB1 and V850/SB2 and design application systems using the V850/SB1 or V850/SB2. Purpose This manual is intended to give users to an understanding of the hardware functions described in the Organization below.
- Page 10 Conventions Data significance: Higher digits on the left and lower digits on the right Active low: xxx (overscore over pin or signal name) Memory map address: Higher addresses at the top and lower addresses at the bottom Note: Footnote for items marked with Note in the text Caution: Information requiring particular attention Remark: Supplementary information Number representation: Binary …...
- Page 11 Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Related documents for V850/SB1 and V850/SB2 Document Name Document No. V850 Series Architecture User’s Manual U10243E V850/SB1, V850/SB2 Hardware User’s Manual This manual Related documents for development tool (user’s manual)
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Page 12: Table Of Contents
Features (V850/SB1 (A versions)) ....................33 1.2.2 Application fields (V850/SB1 (A versions)) .................34 1.2.3 Ordering information (V850/SB1 (A versions))................35 1.2.4 Pin configuration (top view) (V850/SB1 (A versions)) ..............36 1.2.5 Function blocks (V850/SB1 (A versions)) ...................39 V850/SB1 (B Versions) ......................43 1.3.1 Features (V850/SB1 (B versions)) ....................43 1.3.2... - Page 13 3.4.2 Image ............................104 3.4.3 Wrap-around of CPU address space ..................105 3.4.4 Memory map ..........................106 3.4.5 Area ............................107 3.4.6 External expansion mode ......................114 3.4.7 Recommended use of address space ..................117 3.4.8 Peripheral I/O registers ......................119 3.4.9 Specific registers........................
- Page 14 5.3.4 Interrupt control register (xxICn) ....................162 5.3.5 In-service priority register (ISPR) ....................165 5.3.6 ID flag............................165 5.3.7 Watchdog timer mode register (WDTM)..................166 5.3.8 Noise elimination........................166 5.3.9 Edge detection function......................168 Software Exceptions ......................169 5.4.1 Operation ..........................169 5.4.2 Restore............................170 5.4.3 EP flag............................171 Exception Trap ........................171 5.5.1 Illegal opcode definition......................171 5.5.2...
- Page 15 7.2.4 Operation as external event counter..................222 7.2.5 Operation to output square wave....................223 7.2.6 Operation to output one-shot pulse................... 225 7.2.7 Cautions............................ 230 8-Bit Timer (TM2 to TM7)......................234 7.3.1 Outline............................234 7.3.2 Functions ..........................234 7.3.3 Configuration..........................235 7.3.4 Timer n control register ......................
- Page 16 10.3.4 C bus definitions and control methods ..................292 10.3.5 C interrupt requests (INTIICn) ....................299 10.3.6 Interrupt request (INTIICn) generation timing and wait control ..........317 10.3.7 Address match detection method....................318 10.3.8 Error detection...........................318 10.3.9 Extension code..........................318 10.3.10 Arbitration..........................319 10.3.11 Wakeup function ........................320 10.3.12 Communication reservation.......................321 10.3.13 Cautions ............................324 10.3.14 Communication operations......................325...
- Page 17 11.6 Cautions ..........................443 11.7 How to Read A/D Converter Characteristics Table .............447 CHAPTER 12 DMA FUNCTIONS ......................451 12.1 Functions ..........................451 12.2 Transfer Completion Interrupt Request ................451 12.3 Configuration ..........................452 12.4 Control Registers ........................453 12.5 Operation..........................462 12.6 Cautions ..........................463 CHAPTER 13 REAL-TIME OUTPUT FUNCTION (RTO) ..............466 13.1 Function ..........................466 13.2 Features...........................466...
- Page 18 16.2 Operation ..........................517 CHAPTER 17 ROM CORRECTION FUNCTION .................518 17.1 General.............................518 17.2 ROM Correction Peripheral I/O Registers ................519 CHAPTER 18 FLASH MEMORY ......................523 18.1 Features ...........................523 18.1.1 Erase unit ..........................524 18.1.2 Write/read time ..........................524 18.2 Writing with Flash Programmer ....................525 18.3 Programming Environment ....................530 18.4 Communication Mode ......................530 18.5 Pin Connection ........................533...
- Page 19 19.5 Interrupt Generation Timing and Main CPU Processing ............588 19.5.1 Master transmission........................588 19.5.2 Master reception ........................590 19.5.3 Slave transmission........................592 19.5.4 Slave reception ......................... 594 19.5.5 Interval of occurrence of interrupt for IEBus control..............596 CHAPTER 20 ELECTRICAL SPECIFICATIONS .................600 CHAPTER 21 PACKAGE DRAWINGS ....................635 CHAPTER 22...
- Page 20 LIST OF FIGURES (1/6) Figure No. Title Page CPU Register Set ............................97 CPU Address Space.............................103 Image on Address Space ..........................104 Program Space.............................105 Data Space ..............................105 Memory Map..............................106 Internal ROM Area (128 KB).........................107 Internal ROM/Flash Memory Area (256 KB) ....................107 Internal ROM/Flash Memory Area (384 KB) ....................108 3-10 Internal ROM/Flash Memory Area (512 KB) ....................108 3-11...
- Page 21 LIST OF FIGURES (2/6) Figure No. Title Page 5-13 Pipeline Operation at Interrupt Request Acknowledgment................177 5-14 Pipeline Flow and Interrupt Request Signal Generation Timing..............179 5-15 Key Return Block Diagram ........................... 181 Clock Generator ............................183 Oscillation Stabilization Time ........................196 Block Diagram of TM0 and TM1........................
- Page 22 LIST OF FIGURES (3/6) Figure No. Title Page 7-33 Timing of External Event Counter Operation (with Rising Edge Specified) ..........245 7-34 Square Wave Output Operation Timing......................246 7-35 Timing of PWM Output ..........................248 7-36 Timing of Operation Based on CRn0 Transitions ..................249 7-37 Cascade Connection Mode with 16-Bit Resolution..................251 7-38...
- Page 23 LIST OF FIGURES (4/6) Figure No. Title Page 10-28 Address ................................ 354 10-29 Transfer Direction Specification ........................355 10-30 ACK Signal ..............................356 10-31 Stop Condition .............................. 357 10-32 Wait Signal ..............................358 10-33 Arbitration Timing Example .......................... 381 10-34 Communication Reservation Timing......................
- Page 24 LIST OF FIGURES (5/6) Figure No. Title Page 11-7 A/D Conversion End Interrupt Generation Timing ..................445 11-8 Handling of AV Pin ............................446 11-9 Overall Error ..............................447 11-10 Quantization Error............................448 11-11 Zero-Scale Error ............................448 11-12 Full-Scale Error.............................449 11-13 Differential Linearity Error ..........................449 11-14 Integral Linearity Error ..........................450 11-15...
- Page 25 Page 18-1 Wiring Example of V850/SB1 and V850/SB2 Flash Writing Adapter (FA-100GC-8EU)....... 526 18-2 Wiring Example of V850/SB1 and V850/SB2 Flash Writing Adapter (FA-100GF-3BA) ....... 528 18-3 Environment Required for Writing Programs to Flash Memory ..............530 18-4 Communication with Dedicated Flash Programmer (UART0) ..............530 18-5 Communication with Dedicated Flash Programmer (CSI0) ................
- Page 26 Page Product Lineup of V850/SB1 ..........................30 Product Lineup of V850/SB2 ..........................31 Pin I/O Buffer Power Supplies ........................73 Differences in Pins Between V850/SB1 and V850/SB2 .................73 Operating States of Pins in Each Operating Mode ..................80 Program Registers............................98 System Register Numbers..........................99 Interrupt/Exception Table..........................109 Bus Control Pins ............................128...
- Page 27 Setting When Port Pin Is Used as Alternate Function .................. 511 18-1 Table for Wiring of V850/SB1 and V850/SB2 Flash Writing Adapter (FA-100GC-8EU)....... 527 18-2 Table for Wiring of V850/SB1 and V850/SB2 Flash Writing Adapter (FA-100GF-3BA) ....... 529 18-3 Signal Generation of Dedicated Flash Programmer (PG-FP3)..............532 18-4 Pins Used in Serial Interfaces ........................
- Page 28 LIST OF TABLES (3/3) Table No. Title Page 18-7 Response Command ............................540 19-1 Transfer Rate and Maximum Number of Transfer Bytes in Communication Mode 1........542 19-2 Contents of Control Bits..........................547 19-3 Control Field for Locked Slave Unit ......................548 19-4 Control Field for Unlocked Slave Unit......................548 19-5 Acknowledge Signal Output Condition of Control Field ................549 19-6...
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Page 29: Chapter 1 Introduction
ROM/RAM, a timer/counter, a serial interface, an A/D converter, a timer, and DMA controller. Based on the V850/SA1™, the V850/SB1 and V850/SB2 feature various additions, including 3 to 5 V I/O interface support, and ROM correction. For V850/SB2, based on the V850/SB1™, the peripheral functions of automobile LAN (IEBus™... - Page 30 CHAPTER 1 INTRODUCTION Table 1-1. Product Lineup of V850/SB1 Product Name On-Chip RAM Size Package On-Chip IEBus Type Size Commercial Name Part Number µ PD703031A 100-pin QFP (14 × 20)/ V850/SB1 Mask ROM 128 KB 12 KB 100-pin LQFP (14 × 14) µ...
- Page 31 µ PD70F3037H Flash memory µ PD703037HY Mask ROM µ PD70F3037HY Flash memory The part numbers of the V850/SB1 and V850/SB2 are described as follows in this manual. • A versions A versions of the V850/SB1: µ PD703031A, 703031AY, 703032A, 703032AY,...
- Page 32 Flash memory versions of the V850/SB2: µ PD70F3035A, 70F3035AY, 70F3035B, 70F3035BY, 70F3036H, 70F3036HY, 70F3037A, 70F3037AY, 70F3037H, 70F3037HY • Mask ROM versions Mask ROM versions of the V850/SB1: µ PD703030B, 703030BY, 703031A, 703031AY, 703031B, 703031BY, 703032A, 703032AY, 703032B, 703032BY, 703033A, 703033AY, 703033B, 703033BY Mask ROM versions of the V850/SB2: µ...
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Page 33: V850/Sb1 (A Versions)
CHAPTER 1 INTRODUCTION 1.2 V850/SB1 (A Versions) 1.2.1 Features (V850/SB1 (A versions)) Number of instructions: 74 Minimum instruction execution time 50 ns (operating at 20 MHz, external power supply 5 V, regulator output 3.3 V) 32 bits × 32 registers General-purpose registers Signed multiplication (16 ×... -
Page 34: Application Fields (V850/Sb1 (A Versions))
HALT/IDLE/STOP modes 100-pin plastic LQFP (fine pitch, 14 × 14) Package 100-pin plastic QFP (14 × 20) CMOS structure All static circuits 1.2.2 Application fields (V850/SB1 (A versions)) AV equipment Example: Audio, car audio equipment, VCR, and TV. User’s Manual U13850EJ6V0UD... -
Page 35: Ordering Information (V850/Sb1 (A Versions))
CHAPTER 1 INTRODUCTION 1.2.3 Ordering information (V850/SB1 (A versions)) Part Number Package Internal ROM µ PD703031AGC-xxx-8EU 100-pin plastic LQFP (fine pitch) (14 × 14) Mask ROM (128 KB) µ PD703031AGF-xxx-3BA 100-pin plastic QFP (14 × 20) Mask ROM (128 KB) µ... -
Page 36: Pin Configuration (Top View) (V850/Sb1 (A Versions))
CHAPTER 1 INTRODUCTION 1.2.4 Pin configuration (top view) (V850/SB1 (A versions)) 100-pin plastic LQFP (fine pitch) (14 × 14) • µ PD703031AGC-xxx-8EU • µ PD70F3033AGC-8EU • µ PD703031AYGC-xxx-8EU • µ PD70F3033AYGC-8EU • µ PD703033AGC-xxx-8EU • µ PD703033AYGC-xxx-8EU P21/SO2 P71/ANI1 Note 2... - Page 37 CHAPTER 1 INTRODUCTION 100-pin plastic QFP (14 × 20) • µ PD703031AGF-xxx-3BA • µ PD703033AGF-xxx-3BA • µ PD70F3033AGF-3BA • µ PD703031AYGF-xxx-3BA • µ PD703033AYGF-xxx-3BA • µ PD70F3033AYGF-3BA • µ PD703032AGF-xxx-3BA • µ PD70F3032AGF-3BA • µ PD703032AYGF-xxx-3BA • µ PD70F3032AYGF-3BA P14/SO1/TXD0 P73/ANI3 P15/SCK1/ASCK0 P72/ANI2...
- Page 38 CHAPTER 1 INTRODUCTION Pin names (V850/SB1 (A versions)) A1 to A21: Address bus P70 to P77: Port 7 AD0 to AD15: Address/data bus P80 to P83: Port 8 ADTRG: A/D trigger input P90 to P96: Port 9 ANI0 to ANI11:...
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Page 39: Function Blocks (V850/Sb1 (A Versions))
CHAPTER 1 INTRODUCTION 1.2.5 Function blocks (V850/SB1 (A versions)) (1) Internal block diagram HLDRQ (P96) INTC Instruction HLDAK (P95) INTP0 to INTP6 correction queue Note ASTB (P94) DSTB/RD (P93) TI00,TI01, 32-bit barrel Multiplier R/W /WRH (P92) TI10,TI11 Timer/counter shifter 16 ×16→32... - Page 40 CHAPTER 1 INTRODUCTION (2) Internal units (a) CPU The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. Other dedicated on-chip hardware, such as the multiplier (16 bits × 16 bits → 32 bits) and the barrel shifter (32 bits) help accelerate processing of complex instructions.
- Page 41 When used as an interval timer, it generates a maskable interrupt request (INTWDTM) after an overflow occurs. (j) Serial interface (SIO) The V850/SB1 includes three kinds of serial interfaces: asynchronous serial interfaces (UART0, UART1), clocked serial interfaces (CSI0 to CSI3), and an 8-/16-bit variable-length serial interface (CSI4). These plus the I...
- Page 42 CHAPTER 1 INTRODUCTION (n) Ports As shown below, the following ports have general-purpose port functions and control pin functions. Port Port Function Control Function Port 0 8-bit I/O General- NMI, external interrupt, A/D converter trigger, RTP trigger purpose port Port 1 6-bit I/O Serial interface Port 2...
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Page 43: V850/Sb1 (B Versions)
CHAPTER 1 INTRODUCTION 1.3 V850/SB1 (B Versions) 1.3.1 Features (V850/SB1 (B versions)) Number of instructions: 74 Minimum instruction execution time 50 ns (@ 20 MHz operation, external power supply 5 V, regulator output 3.3 V operation) 32 bits × 32 registers General-purpose registers Signed multiplication (16 ×... -
Page 44: Application Fields (V850/Sb1 (B Versions))
HALT/IDLE/STOP modes 100-pin plastic LQFP (fine pitch, 14 × 14) Package 100-pin plastic QFP (14 × 20) CMOS structure All static circuits 1.3.2 Application fields (V850/SB1 (B versions)) AV equipment Example: Audio, car audio equipment, VCR, and TV. User’s Manual U13850EJ6V0UD... -
Page 45: Ordering Information (V850/Sb1 (B Versions))
CHAPTER 1 INTRODUCTION 1.3.3 Ordering information (V850/SB1 (B versions)) Part Number Package Internal ROM µ PD703031BGC-xxx-8EU 100-pin plastic LQFP (fine pitch) (14 × 14) Mask ROM (128 KB) µ PD703031BGF-xxx-3BA 100-pin plastic QFP (14 × 20) Mask ROM (128 KB) µ... -
Page 46: Pin Configuration (Top View) (V850/Sb1 (B Versions))
CHAPTER 1 INTRODUCTION 1.3.4 Pin configuration (top view) (V850/SB1 (B versions)) 100-pin plastic LQFP (fine pitch) (14 × 14) • µ PD703030BGC-xxx-8EU • µ PD703033BGC-xxx-8EU • µ PD70F3033BGC-8EU • µ PD703030BYGC-xxx-8EU • µ PD703033BYGC-xxx-8EU • µ PD70F3033BYGC-8EU • µ PD703031BGC-xxx-8EU •... - Page 47 CHAPTER 1 INTRODUCTION 100-pin plastic QFP (14 × 20) • µ PD703030BGF-xxx-3BA • µ PD703032BGF-xxx-3BA • µ PD70F3030BYGF-3BA • µ PD703030BYGF-xxx-3BA • µ PD703032BYGF-xxx-3BA • µ PD70F3032BGF-3BA • µ PD703031BGF-xxx-3BA • µ PD703033BGF-xxx-3BA • µ PD70F3032BYGF-3BA • µ PD703031BYGF-xxx-3BA • µ PD703033BYGF-xxx-3BA •...
- Page 48 CHAPTER 1 INTRODUCTION Pin names (V850/SB1 (B versions)) A1 to A21: Address bus P70 to P77: Port 7 AD0 to AD15: Address/data bus P80 to P83: Port 8 ADTRG: A/D trigger input P90 to P96: Port 9 ANI0 to ANI11:...
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Page 49: Function Blocks (V850/Sb1 (B Versions))
CHAPTER 1 INTRODUCTION 1.3.5 Function blocks (V850/SB1 (B versions)) (1) Internal block diagram HLDRQ (P96) INTC Instruction HLDAK (P95) INTP0 to INTP6 correction queue Note ASTB (P94) DSTB/RD (P93) TI00,TI01, 32-bit barrel Multiplier R/W /WRH (P92) TI10,TI11 Timer/counter shifter 16 ×16→32... - Page 50 CHAPTER 1 INTRODUCTION (2) Internal units (a) CPU The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. Other dedicated on-chip hardware, such as the multiplier (16 bits × 16 bits → 32 bits) and the barrel shifter (32 bits) help accelerate processing of complex instructions.
- Page 51 When used as an interval timer, it generates a maskable interrupt request (INTWDTM) after an overflow occurs. (j) Serial interface (SIO) The V850/SB1 includes three kinds of serial interfaces: asynchronous serial interfaces (UART0, UART1), clocked serial interfaces (CSI0 to CSI3), and an 8-/16-bit variable-length serial interface (CSI4). These plus the I...
- Page 52 CHAPTER 1 INTRODUCTION (m) Real-time output port (RTP) The RTP is a real-time output function that transfers preset 8-bit data to an output latch when an external trigger signal occurs or when there is a match signal in a timer compare register. It can also be used for 4-bit ×...
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Page 53: V850/Sb2 (A Versions)
CHAPTER 1 INTRODUCTION 1.4 V850/SB2 (A Versions) 1.4.1 Features (V850/SB2 (A versions)) Number of instructions: 74 Minimum instruction execution time 79 ns (operating at 12.58 MHz, external power supply 5 V, regulator output 3.0 V) 32 bits × 32 registers General-purpose registers Signed multiplication (16 ×... -
Page 54: Application Fields (V850/Sb2 (A Versions))
CHAPTER 1 INTRODUCTION C bus interface (I (only for µ PD703034AY, 703035AY, 703037AY, 70F3035AY, and 70F3037AY) 8-/16-bit variable-length serial interface CSI/UART: 2 channels CSI/I 2 channels CSI (8-/16-bit valuable): 1 channel Dedicated baud rate generator: 3 channels A/D converter 10-bit resolution: 12 channels Internal RAM ←→... -
Page 55: Ordering Information (V850/Sb2 (A Versions))
CHAPTER 1 INTRODUCTION 1.4.3 Ordering information (V850/SB2 (A versions)) Part Number Package Internal ROM µ 100-pin plastic LQFP (fine pitch) (14 × 14) PD703034AGC-xxx-8EU Mask ROM (128 KB) µ 100-pin plastic QFP (14 × 20) PD703034AGF-xxx-3BA Mask ROM (128 KB) µ... -
Page 56: Pin Configuration (Top View) (V850/Sb2 (A Versions))
CHAPTER 1 INTRODUCTION 1.4.4 Pin configuration (top view) (V850/SB2 (A versions)) 100-pin plastic LQFP (fine pitch) (14 × 14) • µ PD703034AGC-xxx-8EU • µ PD70F3035AGC-8EU • µ PD703034AYGC-xxx-8EU • µ PD70F3035AYGC-8EU • µ PD703035AGC-xxx-8EU • µ PD703035AYGC-xxx-8EU P21/SO2 P71/ANI1 Note 2 P70/ANI0 P22/SCK2/SCL1 P23/RXD1/SI3... - Page 57 CHAPTER 1 INTRODUCTION 100-pin plastic QFP (14 × 20) • µ PD703034AGF-xxx-3BA • µ PD703037AGF-xxx-3BA • µ PD70F3037AGF-3BA • µ PD703034AYGF-xxx-3BA • µ PD703037AYGF-xxx-3BA • µ PD70F3037AYGF-3BA • µ PD703035AGF-xxx-3BA • µ PD70F3035AGF-3BA • µ PD703035AYGF-xxx-3BA • µ PD70F3035AYGF-3BA P14/SO1/TXD0 P73/ANI3 P15/SCK1/ASCK0 P72/ANI2...
- Page 58 CHAPTER 1 INTRODUCTION Pin names (V850/SB2) A1 to A21: Address bus P70 to P77: Port 7 AD0 to AD15: Address/data bus P80 to P83: Port 8 ADTRG: A/D trigger input P90 to P96: Port 9 ANI0 to ANI11: Analog input P100 to P107: Port 10 ASCK0, ASCK1:...
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Page 59: Function Blocks (V850/Sb2 (A Versions))
CHAPTER 1 INTRODUCTION 1.4.5 Function blocks (V850/SB2 (A versions)) (1) Internal block diagram HLDRQ (P96) INTC Instruction HLDAK (P95) INTP0 to INTP6 correction queue Note ASTB (P94) DSTB/RD (P93) TI00,TI01, 32-bit barrel Multiplier R/W /WRH (P92) TI10,TI11 Timer/counter shifter 16 ×16→32 UBEN (P91) TO0,TO1 16-bit timer:... - Page 60 CHAPTER 1 INTRODUCTION (2) Internal units (a) CPU The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. Other dedicated on-chip hardware, such as the multiplier (16 bits × 16 bits → 32 bits) and the barrel shifter (32 bits) help accelerate processing of complex instructions.
- Page 61 CHAPTER 1 INTRODUCTION (g) Timer/counter A two-channel 16-bit timer/event counter, a four-channel 8-bit timer/event counter, and a two-channel 8- bit interval timer are equipped, enabling measurement of pulse intervals and frequency as well as programmable pulse output. The two-channel 8-bit timer/event counter can be connected via a cascade to enable use as a 16-bit timer.
- Page 62 CHAPTER 1 INTRODUCTION (n) Ports As shown below, the following ports have general-purpose port functions and control pin functions. Port Port Function Control Function Port 0 8-bit I/O General- NMI, external interrupt, A/D converter trigger, RTP trigger purpose port Port 1 6-bit I/O Serial interface Port 2...
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Page 63: V850/Sb2 (B And H Versions)
CHAPTER 1 INTRODUCTION 1.5 V850/SB2 (B and H Versions) 1.5.1 Features (V850/SB2 (B and H versions)) Number of instructions: 74 Minimum instruction execution time B versions: 79 ns (@ 12.58 MHz operation, external power supply 5 V, regulator output 3.0 V operation) H versions: 53 ns (@ 18.87 MHz operation, external power supply 5 V, regulator output 3.3 V operation) 32 bits ×... -
Page 64: Application Fields (V850/Sb2 (B And H Versions))
CHAPTER 1 INTRODUCTION Watch timer When operating under subclock or main clock: 1 channel Operation using the subclock or main clock is also possible in the IDLE mode. Watchdog timer 1 channel Serial interface (SIO) Asynchronous serial interface (UART) Clocked serial interface (CSI) C bus interface (I (only for µ... -
Page 65: Ordering Information (V850/Sb2 (B And H Versions))
CHAPTER 1 INTRODUCTION 1.5.3 Ordering information (V850/SB2 (B and H versions)) Part Number Package Internal ROM µ 100-pin plastic LQFP (fine pitch) (14 × 14) PD703034BGC-xxx-8EU Mask ROM (128 KB) µ 100-pin plastic QFP (14 × 20) PD703034BGF-xxx-3BA Mask ROM (128 KB) µ... -
Page 66: Pin Configuration (Top View) (V850/Sb2 (B And H Versions))
CHAPTER 1 INTRODUCTION 1.5.4 Pin configuration (top view) (V850/SB2 (B and H versions)) 100-pin plastic LQFP (fine pitch) (14 × 14) • µ PD703034BGC-xxx-8EU • µ PD703036HGC-xxx-8EU • µ PD70F3036HGC-8EU • µ PD703034BYGC-xxx-8EU • µ PD703036HYGC-xxx-8EU • µ PD70F3036HYGC-8EU • µ PD703035BGC-xxx-8EU •... - Page 67 CHAPTER 1 INTRODUCTION 100-pin plastic QFP (14 × 20) • µ PD703034BGF-xxx-3BA • µ PD703036HGF-xxx-3BA • µ PD70F3035BYGF-3BA • µ PD703034BYGF-xxx-3BA • µ PD703036HYGF-xxx-3BA • µ PD70F3036HGF-xxx-3BA • µ PD703035BGF-xxx-3BA • µ PD703037HGF-xxx-3BA • µ PD70F3036HYGF-xxx-3BA • µ PD703035BYGF-xxx-3BA • µ PD703037HYGF-xxx-3BA •...
- Page 68 CHAPTER 1 INTRODUCTION Pin names (V850/SB2 (B and H versions)) A1 to A21: Address bus P70 to P77: Port 7 AD0 to AD15: Address/data bus P80 to P83: Port 8 ADTRG: A/D trigger input P90 to P96: Port 9 ANI0 to ANI11: Analog input P100 to P107: Port 10...
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Page 69: Function Blocks (V850/Sb2 (B And H Versions))
CHAPTER 1 INTRODUCTION 1.5.5 Function blocks (V850/SB2 (B and H versions)) (1) Internal block diagram HLDRQ (P96) INTC Instruction HLDAK (P95) INTP0 to INTP6 correction queue Note ASTB (P94) DSTB/RD (P93) TI00,TI01, 32-bit barrel Multiplier R/W /WRH (P92) TI10,TI11 Timer/counter shifter 16 ×16→32 UBEN (P91) - Page 70 CHAPTER 1 INTRODUCTION (2) Internal units (a) CPU The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. Other dedicated on-chip hardware, such as the multiplier (16 bits × 16 bits → 32 bits) and the barrel shifter (32 bits) help accelerate processing of complex instructions.
- Page 71 CHAPTER 1 INTRODUCTION (f) Clock generator (CG) The clock generator includes two types of oscillators; each for main clock (f ) and for subclock (f generates five types of clocks (f /2, f /4, f /8, and f ), and supplies one of them as the operating clock for the CPU (f (g) Timer/counter A two-channel 16-bit timer/event counter, a four-channel 8-bit timer/event counter, and a two-channel 8-...
- Page 72 CHAPTER 1 INTRODUCTION (m) Real-time output port (RTP) The RTP is a real-time output function that transfers preset 8-bit data to an output latch when an external trigger signal occurs or when there is a match signal in a timer compare register. It can also be used for 4-bit ×...
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Page 73: Chapter 2 Pin Functions
PIN FUNCTIONS 2.1 List of Pin Functions The names and functions of the pins of the V850/SB1 and V850/SB2 are described below divided into port pins and non-port pins. There are three types of power supplies for the pin I/O buffers: AV... - Page 74 CHAPTER 2 PIN FUNCTIONS (1) Port pins (1/3) Pin Name PULL Function Alternate Function Port 0 8-bit I/O port INTP0 Input/output mode can be specified in 1-bit units. INTP1 INTP2 INTP3 INTP4/ADTRG INTP5/RTPTRG INTP6 Port 1 SI0/SDA0 6-bit I/O port Input/output mode can be specified in 1-bit units.
- Page 75 CHAPTER 2 PIN FUNCTIONS (2/3) Pin Name PULL Function Alternate Function Port 3 TI00 8-bit I/O port TI01 Input/output mode can be specified in 1-bit units. TI10/SI4 TI11/SO4 TO0/A13/SCK4 TO1/A14 TI4/TO4/A15 TI5/TO5 Port 4 8-bit I/O port Input/output mode can be specified in 1-bit units. Port 5 8-bit I/O port Input/output mode can be specified in 1-bit units.
- Page 76 CHAPTER 2 PIN FUNCTIONS (3/3) Pin Name PULL Function Alternate Function Input Port 7 ANI0 8-bit input port ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 Input Port 8 ANI8 4-bit input port ANI9 ANI10 ANI11 Port 9 LBEN/WRL 7-bit I/O port UBEN Input/output mode can be specified in 1-bit units.
- Page 77 CHAPTER 2 PIN FUNCTIONS (2) Non-port pins (1/3) Pin Name PULL Function Alternate Function Output Lower address bus used for external memory expansion P110/WAIT A2 to A4 P111 to P113 A5 to A8 P100/RTP0/KR0 to P103/RTP3/KR3 P104/RTP4/KR4/IERX P105/RTP5/KR5/IETX A11, A12 P106/RTP6/KR6 to P107/RTP7/KR7 P34/TO0/SCK4...
- Page 78 CHAPTER 2 PIN FUNCTIONS (2/3) Pin Name PULL Function Alternate Function INTP6 Input External interrupt request input (digital noise elimination for remote control) KR0 to KR3 Key return input P100/A5/RTP0 to P103/A8/RTP3 P104/A9/RTP4/IERX P105/A10/RTP5/IETX KR6, KR7 P106/A11/RTP6 to P107/A12/RTP7 LBEN Output External data bus’s lower byte enable signal output P90/WRL...
- Page 79 CHAPTER 2 PIN FUNCTIONS (3/3) Pin Name PULL Function Alternate Function Output Serial transmit data output (3-wire type) for CSI0 to CSI3 P14/TXD0 P24/TXD1 Serial transmit data output for variable-length CSI4 (3-wire type) P33/TI11 TI00 Input Shared as external capture trigger input and external count clock input for TM0 TI01 External capture trigger input for TM0...
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Page 80: Pin States
CHAPTER 2 PIN FUNCTIONS 2.2 Pin States The operating states of various pins are described below with reference to their operating modes. Table 2-3. Operating States of Pins in Each Operating Mode Note 1 Operating State Reset HALT Mode/ IDLE Mode/ Bus Hold Bus Cycle Note 2... -
Page 81: Description Of Pin Functions
CHAPTER 2 PIN FUNCTIONS 2.3 Description of Pin Functions (1) P00 to P07 (Port 0) ··· 3-state I/O P00 to P07 constitute an 8-bit I/O port that can be set to input or output in 1-bit units. P00 to P07 can also function as an NMI input, external interrupt request inputs, external trigger for the A/D converter, and external trigger for the real-time output port. - Page 82 CHAPTER 2 PIN FUNCTIONS (2) P10 to P15 (Port 1) ··· 3-state I/O P10 to P15 constitute a 6-bit I/O port that can be set to input or output in 1-bit units. P10 to P15 can also function as input or output pins for the serial interface. P10 to P12, P14, and P15 can be selected as normal output or N-ch open-drain output.
- Page 83 CHAPTER 2 PIN FUNCTIONS (3) P20 to P27 (Port 2) ··· 3-state I/O P20 to P27 constitute an 8-bit I/O port that can be set to input or output in 1-bit units. P20 to P27 can also function as input or output pins for the serial interface, and input or output pins for the timer/counter.
- Page 84 CHAPTER 2 PIN FUNCTIONS (4) P30 to P37 (Port 3) ··· 3-state I/O P30 to P37 constitute an 8-bit I/O port that can be set to input or output in 1-bit units. P30 to P37 can also function as input or output pins for the timer/counter, an address bus (A13 to A15) when memory is expanded externally, and serial interface I/O.
- Page 85 CHAPTER 2 PIN FUNCTIONS (5) P40 to P47 (Port 4) ··· 3-state I/O P40 to P47 constitute an 8-bit I/O port that can be set to input or output pins in 1-bit units. P40 to P47 can also function as a time division address/data bus (AD0 to AD7) when memory is expanded externally.
- Page 86 CHAPTER 2 PIN FUNCTIONS (7) P60 to P65 (Port 6) ··· 3-state I/O P60 to P65 constitute a 6-bit I/O port that can be set to input or output in 1-bit units. P60 to P65 can also function as an address bus (A16 to A21) when memory is expanded externally. When the port 6 is accessed in 8-bit units, the higher 2 bits of port 6 are ignored when they are written to and 00 is read when they are read.
- Page 87 CHAPTER 2 PIN FUNCTIONS (9) P90 to P96 (Port 9) ··· 3-state I/O P90 to P96 constitute a 7-bit I/O port that can be set to input or output pins in 1-bit units. P90 to P96 can also function as control signal output pins and bus hold control signal output pins when memory is expanded externally.
- Page 88 (vii) HLDRQ (Hold request) ··· input This is an input pin by which an external device requests the V850/SB1 and V850/SB2 to release the address bus, data bus, and control bus. This pin accepts asynchronous input for CLKOUT. When this pin is active, the address bus, data bus, and control bus are set to high impedance status.
- Page 89 CHAPTER 2 PIN FUNCTIONS (10) P100 to P107 (Port 10) ··· 3-state I/O P100 to P107 constitute an 8-bit I/O port that can be set to input or output in 1-bit units. P100 to P107 can also function as a real-time output port, an address bus (A5 to A12) when memory is expanded externally, key return input, and IEBus data I/O (V850/SB2 only).
- Page 90 CHAPTER 2 PIN FUNCTIONS (11) P110 to P113 (Port 11) ··· 3-state I/O P110 to P113 constitute a 4-bit I/O port that can be set to input or output in 1-bit units. P110 to P113 can also function as an address bus (A1 to A4) when memory is expanded externally, signal (WAIT) that inserts waits into the bus cycle and a control.
- Page 91 CHAPTER 2 PIN FUNCTIONS (18) AV (Analog V This is the ground pin for the A/D converter or alternate-function port. (19) AV (Analog reference voltage) … input This is the reference voltage supply pin for the A/D converter. (20) BV (Power supply for bus interface) This is the positive power supply pin for the bus interface and its alternate-function ports.
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Page 92: Pin I/O Circuit Types, I/O Buffer Power Supplies And Connection Of Unused Pins
CHAPTER 2 PIN FUNCTIONS 2.4 Pin I/O Circuit Types, I/O Buffer Power Supplies and Connection of Unused Pins (1/2) Alternate Function I/O Circuit Type Recommended Connection Method Buffer Power Supply Input: Independently connect to EV or EV via a resistor Output: Leave open P01 to P04 INTP0 to INTP3... - Page 93 CHAPTER 2 PIN FUNCTIONS (2/2) Alternate Function I/O Circuit Type Recommended Connection Method Buffer Power Supply LBEN/WRL Input: Independently connect to EV or EV via a resistor Output: Leave open UBEN R/W/WRH DSTB/RD ASTB HLDAK HLDRQ P100 to P103 RTP0/A5/KR0 to 10-A Input: Independently connect to EV...
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Page 94: Pin I/O Circuits
CHAPTER 2 PIN FUNCTIONS 2.5 Pin I/O Circuits (1/2) Type 2 Type 5-A Pullup P-ch enable Data P-ch IN/OUT Schmitt-triggered input with hysteresis characteristics Output N-ch disable Input enable Type 4 Type 8-A Data P-ch Pullup P-ch enable Data P-ch IN/OUT Output N-ch... - Page 95 CHAPTER 2 PIN FUNCTIONS (2/2) Type 10-A Type 26 Pullup Pullup P-ch P-ch enable enable Data Data P-ch P-ch IN/OUT IN/OUT Open drain Open drain N-ch N-ch Output disable Output disable Type 16 Feedback cut-off P-ch User’s Manual U13850EJ6V0UD...
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Page 96: Chapter 3 Cpu Functions
CHAPTER 3 CPU FUNCTIONS The CPU of the V850/SB1 and V850/SB2 is based on RISC architecture and executes most instructions in one clock cycle by using a 5-stage pipeline. 3.1 Features • Minimum instruction execution time V850/SB1 (A version, B version): 50 ns (@20 MHz internal operation) V850/SB2 (A version, B version): 79 ns (@12.58 MHz internal operation) -
Page 97: Cpu Register Set
3.2 CPU Register Set The CPU registers of the V850/SB1 and V850/SB2 can be classified into two categories: a general-purpose program register set and a dedicated system register set. All the registers are 32 bits wide. For details, refer to V850 Series Architecture User’s Manual... -
Page 98: Program Register Set
CHAPTER 3 CPU FUNCTIONS 3.2.1 Program register set The program register set includes general-purpose registers and a program counter. (1) General-purpose registers Thirty-two general-purpose registers, r0 to r31, are available. Any of these registers can be used as a data variable or address variable. -
Page 99: System Register Set
CHAPTER 3 CPU FUNCTIONS 3.2.2 System register set System registers control the status of the CPU and hold interrupt information. Table 3-2. System Register Numbers System Register Name Usage Operation EIPC Interrupt status saving registers These registers save the PC and PSW when an exception or interrupt occurs. - Page 100 CHAPTER 3 CPU FUNCTIONS (2) Program status word (PSW) (1/2) After reset: 00000020H ID SAT CY OV Reserved field (fixed to 0). Non-maskable interrupt (NMI) servicing status NMI servicing not under execution. NMI servicing under execution. This flag is set (1) when an NMI is acknowledged, and disables multiple interrupts.
- Page 101 CHAPTER 3 CPU FUNCTIONS (2/2) Note Detection of operation result positive/negative The operation result was positive or 0. The operation result was negative. Detection of operation result zero The operation result was not 0. The operation result was 0. Note The result of a saturation-processed operation is determined by the contents of the OV and S bits in the saturation operation.
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Page 102: Operation Modes
CPU FUNCTIONS 3.3 Operation Modes The V850/SB1 and V850/SB2 have the following operation modes. (1) Normal operation mode (single-chip mode) After the system has been released from the reset status, the pins related to the bus interface are set for port mode, execution branches to the reset entry address of the internal ROM, and instruction processing written in the internal ROM is started. -
Page 103: Address Space
3.4 Address Space 3.4.1 CPU address space The CPUs of the V850/SB1 and V850/SB2 are of 32-bit architecture and support up to 4 GB of linear address space (data space) during operand addressing (data access). When referencing instruction addresses, linear address space (program space) of up to 16 MB is supported. -
Page 104: Image
CHAPTER 3 CPU FUNCTIONS 3.4.2 Image The core CPU supports 4 GB of “virtual” addressing space, or 256 memory blocks, each containing 16 MB memory locations. In actuality, the same 16 MB block is accessed regardless of the values of bits 31 to 24 of the CPU address. -
Page 105: Wrap-Around Of Cpu Address Space
CHAPTER 3 CPU FUNCTIONS 3.4.3 Wrap-around of CPU address space (1) Program space Of the 32 bits of the PC (program counter), the higher 8 bits are fixed to 0, and only the lower 24 bits are valid. Even if a carry or borrow occurs from bit 23 to 24 as a result of branch address calculation, the higher 8 bits ignore the carry or borrow and remain 0. -
Page 106: Memory Map
CHAPTER 3 CPU FUNCTIONS 3.4.4 Memory map The V850/SB1 and V850/SB2 reserve areas as shown below. Figure 3-6. Memory Map Single-chip mode Single-chip mode (external expansion mode) xxFFFFFFH On-chip peripheral On-chip peripheral 4 KB I/O area I/O area xxFFF000H xxFFEFFFH... -
Page 107: Area
(1) Internal ROM/flash memory area An area of 1 MB maximum is reserved for the internal ROM/flash memory area. (a) V850/SB1 ( µ µ µ µ PD703031A, 703031AY, 703031B, 703031BY) V850/SB2 ( µ µ µ µ PD703034A, 703034AY, 703034B, 703034BY) 128 KB are available for the addresses xx000000H to xx01FFFFH. -
Page 108: Internal Rom/Flash Memory Area (384 Kb)
CHAPTER 3 CPU FUNCTIONS (c) V850/SB1 ( µ µ µ µ PD703030B, 703030BY, 70F3030B, 70F3030BY) V850/SB2 ( µ µ µ µ PD703036H, 703036HY, 70F3036H, 70F3036HY) 384 KB are available for the addresses xx000000H to xx05FFFFH. Addresses xx060000H to xx0FFFFFH are an access-prohibited area Figure 3-9. - Page 109 CHAPTER 3 CPU FUNCTIONS Interrupt/exception table The V850/SB1 and V850/SB2 increase the interrupt response speed by assigning handler addresses corresponding to interrupts/exceptions. The collection of these handler addresses is called an interrupt/exception table, which is located in the internal ROM area. When an interrupt/exception request is granted, execution jumps to the handler address, and the program written at that memory address is executed.
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Page 110: Internal Ram Area (8 Kb)
An area of 28 KB maximum is reserved for the internal RAM area. (a) V850/SB1 ( µ µ µ µ PD703031B, 703031BY), V850/SB2 ( µ µ µ µ PD703034B, 703034BY) 8 KB are available for the addresses xxFFD000H to xxFFEFFFH. -
Page 111: Internal Ram Area (16 Kb)
CHAPTER 3 CPU FUNCTIONS (c) V850/SB1 ( µ µ µ µ PD703033A, 703033AY, 70F3033A, 70F3033AY, 703033B, 703033BY, 70F3033B, 70F3033BY) V850/SB2 ( µ µ µ µ PD703035A, 703035AY, 70F3035A, 70F3035AY, 703035B, 703035BY, 70F3035B, 70F3035BY) 16 KB are available for the addresses xxFFB000H to xxFFEFFFH. -
Page 112: On-Chip Peripheral I/O Area
(3) On-chip peripheral I/O area A 4 KB area of addresses FFF000H to FFFFFFH is reserved as an on-chip peripheral I/O area. The V850/SB1 and V850/SB2 are provided with a 1 KB area of addresses FFF000H to FFF3FFH as a physical on-chip peripheral I/O area, and its image can be seen on the rest of the area (FFF400H to FFFFFFH). -
Page 113: External Memory Area (When Expanded To 64 K, 256 K, Or 1 Mb)
CPU FUNCTIONS (4) External memory The V850/SB1 and V850/SB2 can use an area of up to 16 MB (xx100000H to xxFF7FFFH) for external memory accesses (in single-chip mode: external expansion). 64 K, 256 K, 1 M, or 4 MB of physical external memory can be allocated when the external expansion mode is specified. -
Page 114: External Expansion Mode
3.4.6 External expansion mode The V850/SB1 and V850/SB2 allow external devices to be connected to the external memory space by using the pins of ports 4, 5, 6, and 9. To connect an external device, the port pins must be set in the external expansion mode by using the memory expansion mode register (MM). - Page 115 CHAPTER 3 CPU FUNCTIONS (1) Memory expansion mode register (MM) This register sets the mode of each pin of ports 4, 5, 6, and 9. In the external expansion mode, an external device can be connected to the external memory area of up to 4 MB. However, the external device cannot be connected to the internal RAM area, on-chip peripheral I/O area, and internal ROM area in the single-chip mode (and even if the external device is connected physically, it cannot be accessed).
- Page 116 CHAPTER 3 CPU FUNCTIONS (2) Memory address output mode register (MAM) Sets the mode of ports 3, 10, and 11. Separate output can be set for the address bus (A1 to A15) in the external expansion mode. The MAM register can be written in 8-bit units. If read is performed, undefined values will be read. However, bits 3 to 7 are fixed to 0.
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Page 117: Recommended Use Of Address Space
8 MB address spaces 00000000H to 007FFFFFH and FF800000H to FFFFFFFFH of the 4 GB CPU are used as the data space. With the V850/SB1 or V850/SB2, 16 MB physical address space is seen as 256 images in the 4 GB CPU address space. The highest bit (bit 23) of this 24-bit address is assigned as address sign-extended to 32 bits. -
Page 118: Recommended Memory Map (Flash Memory Version)
Note This area cannot be used as a program area. Remarks 1. The arrows indicate the recommended area. 2. This is a recommended memory map for V850/SB1 ( µ PD70F3033A, 70F3033AY, 70F3033B, 70F3033BY), V850/SB2 ( µ PD70F3035A, 70F3035AY, 70F3035B, 70F3035BY). -
Page 119: Peripheral I/O Registers
CHAPTER 3 CPU FUNCTIONS 3.4.8 Peripheral I/O registers (1/7) Address Function Register Name Symbol Bit Units for Manipulation After Reset 1 Bit 8 Bits 16 Bits 32 Bits Note √ √ FFFFF000H Port 0 √ √ FFFFF002H Port 1 √ √... - Page 120 CHAPTER 3 CPU FUNCTIONS (2/7) Address Function Register Name Symbol Bit Units for Manipulation After Reset 1 Bit 8 Bits 16 Bits 32 Bits √ √ FFFFF096H Pull-up resistor option register 11 PU11 √ √ FFFFF0A2H Port 1 function register √...
- Page 121 CHAPTER 3 CPU FUNCTIONS (3/7) Address Function Register Name Symbol Bit Units for Manipulation After Reset 1 Bit 8 Bits 16 Bits 32 Bits √ √ FFFFF140H Interrupt control register CSIC4 Note √ √ FFFFF142H Interrupt control register IEBIC1 Note √...
- Page 122 CHAPTER 3 CPU FUNCTIONS (4/7) Address Function Register Name Symbol Bit Units for Manipulation After Reset 1 Bit 8 Bits 16 Bits 32 Bits √ FFFFF1D4H DMA byte count register 5 DBC5 Undefined √ √ FFFFF1D6H DMA channel control register 5 DCHC5 √...
- Page 123 CHAPTER 3 CPU FUNCTIONS (5/7) Address Function Register Name Symbol Bit Units for Manipulation After Reset 1 Bit 8 Bits 16 Bits 32 Bits √ FFFFF26AH 16-bit counter 45 (during cascade connection TM45 0000H only) √ FFFFF26CH 16-bit compare register 45 (during cascade CR45 connection only) √...
- Page 124 CHAPTER 3 CPU FUNCTIONS (6/7) Address Function Register Name Symbol Bit Units for Manipulation After Reset 1 Bit 8 Bits 16 Bits 32 Bits √ √ FFFFF2E2H Variable-length serial control register 4 CSIM4 √ √ FFFFF2E4H Variable-length serial setting register 4 CSIB4 √...
- Page 125 IEBus transfer counter V850/SB2 CCR √ FFFFF3F8H IEBus clock selection register V850/SB2 IECLK Notes 1. Available only in the B versions of the V850/SB1 and H versions of the V850/SB2. Available only in the H versions of the V850/SB2. User’s Manual U13850EJ6V0UD...
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Page 126: Specific Registers
The write access of these specific registers is executed in a specific sequence, and if abnormal store operations occur, it is notified by the system status register (SYS). The V850/SB1 and V850/SB2 have two specific registers, the power save control register (PSC) and processor clock control register (PCC). For details of the PSC register, refer to 6.3.1 (2) Power save control register (PSC), and for details of the PCC register, refer to 6.3.1 (1) - Page 127 CHAPTER 3 CPU FUNCTIONS (1) Command register (PRCMD) The command register (PRCMD) is a register used when write-accessing the specific register to prevent incorrect writing to the specific registers due to the erroneous program execution. This register can be written in 8-bit units. It becomes undefined values in a read cycle. Occurrence of illegal store operations can be checked by the PRERR bit of the SYS register.
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Page 128: Chapter 4 Bus Control Function
CHAPTER 4 BUS CONTROL FUNCTION The V850/SB1 and V850/SB2 are provided with an external bus interface function by which external memories such as ROM and RAM, and I/O can be connected. 4.1 Features • Address bus (capable of separate output) •... -
Page 129: Control Register
(MM)). Caution In the V850/SB1 and V850/SB2, when using port 9 as an I/O port, set the BIC bit of the system control register (SYC) to 0. Note that the BIC bit is 0 after system reset. -
Page 130: Bus Width
CHAPTER 4 BUS CONTROL FUNCTION 4.3.2 Bus width The CPU carries out peripheral I/O access and external memory access in 8-bit, 16-bit, or 32-bit units. The following shows the operation for each access. (1) Byte access (8 bits) Byte access is divided into two types, access to even addresses and access to odd addresses. Figure 4-1. -
Page 131: Memory Block Function
CHAPTER 4 BUS CONTROL FUNCTION 4.4 Memory Block Function The 16 MB memory space is divided into memory blocks of 1 MB units. The programmable wait function and bus cycle operation mode can be independently controlled for every two memory blocks. Figure 4-4. -
Page 132: Wait Function
CHAPTER 4 BUS CONTROL FUNCTION 4.5 Wait Function 4.5.1 Programmable wait function To facilitate interfacing with low-speed memories and I/O devices, up to 3 data waits can be inserted in a bus cycle that starts every two memory blocks. The number of waits can be programmed by using the data wait control register (DWC). Immediately after the system has been reset, a state in which three data waits are inserted is automatically programmed for all memory blocks. -
Page 133: External Wait Function
CHAPTER 4 BUS CONTROL FUNCTION 4.5.2 External wait function When an extremely slow device, I/O, or asynchronous system is connected, any number of wait states can be inserted in the bus cycle by sampling the external wait pin (WAIT) to synchronize with the external device. The external wait signal is data wait only, and does not affect the access times of the internal ROM, internal RAM, and on-chip peripheral I/O areas, similar to programmable wait. -
Page 134: Idle State Insertion Function
CHAPTER 4 BUS CONTROL FUNCTION 4.6 Idle State Insertion Function To facilitate interfacing with low-speed memory devices and meeting the data output float delay time on memory read accesses every two blocks, one idle state (TI) can be inserted into the current bus cycle after the T3 state. The following bus cycle starts after one idle state. -
Page 135: Bus Hold Function
CHAPTER 4 BUS CONTROL FUNCTION 4.7 Bus Hold Function 4.7.1 Outline of function When the MM3 bit of the memory expansion mode register (MM) is set (1), the HLDRQ and HLDAK pin functions of P95 and P96 become valid. When the HLDRQ pin becomes active (low) indicating that another bus master is requesting acquisition of the bus, Note the external address/data bus and strobe pins go into a high-impedance state , and the bus is released (bus hold... -
Page 136: Bus Hold Procedure
CHAPTER 4 BUS CONTROL FUNCTION 4.7.2 Bus hold procedure The procedure of the bus hold function is illustrated below. Figure 4-7. Bus Hold Procedure <1>HLDRQ = 0 acknowledged Normal status <2>All bus cycle start requests held pending <3>End of current bus cycle <4>Bus idle status <5>HLDAK = 0 Bus hold status... -
Page 137: Bus Timing
BUS CONTROL FUNCTION 4.8 Bus Timing The V850/SB1 and V850/SB2 can execute read/write control for an external device using the following two modes. • Mode using DSTB, R/W, LBEN, UBEN, and ASTB signals • Mode using RD, WRL, WRH, and ASTB signals Set these modes by using the BIC bit of the system control register (SYC) (see 4.2.2 (1) System control register... - Page 138 CHAPTER 4 BUS CONTROL FUNCTION Figure 4-8. Memory Read (2/4) (b) 1 wait CLKOUT (output) A16 to A21 (output) Address A1 to A15 (output) Address Address AD0 to AD15 (I/O) Data ASTB (output) R/W (output) WRH, WRL (output) DSTB, RD (output) UBEN, LBEN (output) WAIT (input) Remarks 1.
- Page 139 CHAPTER 4 BUS CONTROL FUNCTION Figure 4-8. Memory Read (3/4) (c) 0 waits, idle state CLKOUT (output) Address A16 to A21 (output) Address A1 to A15 (output) Address Data AD0 to AD15 (I/O) ASTB (output) R/W (output) WRH, WRL (output) DSTB, RD (output) UBEN, LBEN (output) WAIT (input)
- Page 140 CHAPTER 4 BUS CONTROL FUNCTION Figure 4-8. Memory Read (4/4) (d) 1 wait, idle state CLKOUT (output) Address A16 to A21 (output) Address A1 to A15 (output) AD0 to AD15 (I/O) Address Data ASTB (output) R/W (output) WRH, WRL (output) DSTB, RD (output) UBEN, LBEN (output) WAIT (input)
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Page 141: Memory Write
CHAPTER 4 BUS CONTROL FUNCTION Figure 4-9. Memory Write (1/2) (a) 0 waits CLKOUT (output) Address A16 to A21 (output) Address A1 to A15 (output) Note Address Data AD0 to AD15 (I/O) ASTB (output) R/W (output) RD (output) DSTB (output) WRH, WRL (output) UBEN, LBEN (output) WAIT (input) - Page 142 CHAPTER 4 BUS CONTROL FUNCTION Figure 4-9. Memory Write (2/2) (b) 1 wait CLKOUT (output) Address A16 to A21 (output) A1 to A15 (output) Address Note Address Data AD0 to AD15 (I/O) ASTB (output) R/W (output) RD (output) DSTB (output) WRH, WRL (output) UBEN, LBEN (output) WAIT (input)
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Page 143: Bus Hold Timing
CHAPTER 4 BUS CONTROL FUNCTION Figure 4-10. Bus Hold Timing CLKOUT (output) HLDRQ (input) Note 1 HLDAK (output) A16 to A21 (output) Address Address A1 to A15 (output) Address Address AD0 to AD15 (I/O) Undefined Address Data Address ASTB (output) Note 2 R/W (output) DSTB, RD,... -
Page 144: Bus Priority
CHAPTER 4 BUS CONTROL FUNCTION 4.9 Bus Priority There are four external bus cycles: bus hold, memory access, instruction fetch (branch), and instruction fetch (continuous). The bus hold cycle is given the highest priority, followed by memory access, instruction fetch (branch), and instruction fetch (continuous) in that order. -
Page 145: Memory Boundary Operation Conditions
CHAPTER 4 BUS CONTROL FUNCTION 4.10 Memory Boundary Operation Conditions 4.10.1 Program space (1) Do not execute a branch to the on-chip peripheral I/O area or continuous fetch from the internal RAM area to the peripheral I/O area. If a branch or instruction fetch is executed, the NOP instruction code is continuously fetched and no data is fetched from external memory. -
Page 146: Chapter 5 Interrupt/Exception Processing Function
INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.1 Outline The V850/SB1 and V850/SB2 are provided with a dedicated interrupt controller (INTC) for interrupt servicing and realize a high-powered interrupt function that can service interrupt requests from a total of 37 to 40 sources. An interrupt is an event that occurs independently of program execution, and an exception is an event that is dependent on program execution. - Page 147 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 5-1. Interrupt Source List (1/2) Type Classifi- Default Name Trigger Interrupt Exception Handler Restored Interrupt cation Priority Source Code Address Control Register − − − Reset Interrupt RESET Reset input 0000H 00000000H Unde- fined −...
- Page 148 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 5-1. Interrupt Source List (2/2) Type Classifi- Default Name Trigger Interrupt Exception Handler Restored Interrupt cation Priority Source Code Address Control Register Maskable Interrupt INTCSI2 CSI2 transmit end CSI2 0230H 00000230H nextPC CSIC2 Note 1 INTIIC1 C1 interrupt 0240H...
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Page 149: Non-Maskable Interrupt
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.2 Non-Maskable Interrupt A non-maskable interrupt is acknowledged unconditionally, even when interrupts are disabled (DI state). An NMI is not subject to priority control and takes precedence over all other interrupts. The following two non-maskable interrupt requests are available in the V850/SB2. •... -
Page 150: Operation
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.2.1 Operation If a non-maskable interrupt is generated, the CPU performs the following processing, and transfers control to the handler routine. (1) Saves the restored PC to FEPC. (2) Saves the current PSW to FEPSW. (3) Writes exception codes 0010H and 0020H to the higher halfword (FECC) of ECR. -
Page 151: Acknowledging Non-Maskable Interrupt Request
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 5-2. Acknowledging Non-Maskable Interrupt Request (a) If a new NMI request is generated while an NMI service routine is being executed: Main routine (PSW. NP = 1) NMI request NMI request NMI request held pending because PSW. NP = 1 Pending NMI request processed (b) If a new NMI request is generated twice while an NMI service routine is being executed: Main routine... -
Page 152: Restore
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.2.2 Restore Execution is restored from non-maskable interrupt servicing by the RETI instruction. Operation of RETI instruction When the RETI instruction is executed, the CPU performs the following processing, and transfers control to the address of the restored PC. (1) Restores the values of the PC and PSW from FEPC and FEPSW, respectively, because the EP bit of the PSW is 0 and the NP bit of the PSW is 1. -
Page 153: Np Flag
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.2.3 NP flag The NP flag is a status flag that indicates that non-maskable interrupt (NMI) servicing is under execution. This flag is set when an NMI interrupt request has been acknowledged, and masks all interrupt requests to prohibit multiple interrupts from being acknowledged. -
Page 154: Edge Detection Function Of Nmi Pin
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.2.5 Edge detection function of NMI pin The NMI pin valid edge can be selected from the following four types: falling edge, rising edge, both edges, or neither edge. Rising edge specification register 0 (EGP0) and falling edge specification register 0 (EGN0) specify the valid edge of the non-maskable interrupt (NMI). -
Page 155: Maskable Interrupts
INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.3 Maskable Interrupts Maskable interrupt requests can be masked by interrupt control registers. The V850/SB1 and V850/SB2 have 37 to 40 maskable interrupt sources (see 5.1.1 Features). If two or more maskable interrupt requests are generated at the same time, they are acknowledged according to the default priority. -
Page 156: Maskable Interrupt Servicing
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 5-4. Maskable Interrupt Servicing INT input INTC accepted Mask? PSW. ID = 0 Interrupt enable mode? Priority higher than that of interrupt currently serviced? Priority higher than that of other interrupt request? Highest default priority of interrupt requests with the same priority? Maskable interrupt request... -
Page 157: Restore
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.3.2 Restore To restore execution from maskable interrupt servicing, the RETI instruction is used. Operation of RETI instruction When the RETI instruction is executed, the CPU performs the following steps, and transfers control to the address of the restored PC. -
Page 158: Priorities Of Maskable Interrupts
INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.3.3 Priorities of maskable interrupts The V850/SB1 and V850/SB2 provide multiple interrupt servicing in which an interrupt is acknowledged while another interrupt is being serviced. Multiple interrupts can be controlled by priority levels. There are two types of priority level control: control based on the default priority levels, and control based on the programmable priority levels which are specified by the interrupt priority level specification bit (xxPRn). -
Page 159: Example Of Multiple Interrupt Servicing
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 5-6. Example of Multiple Interrupt Servicing (1/2) Main routine Servicing of a Servicing of b Interrupt Interrupt request a request b Interrupt request b is acknowledged because the priority of (level 3) (level 2) b is higher than that of a and interrupts are enabled. - Page 160 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 5-6. Example of Multiple Interrupt Servicing (2/2) Main routine Servicing of i Processing of k Interrupt request j Interrupt request i (level 3) (level 2) Interrupt request j is held pending because its Interrupt request k priority is lower than that of i.
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Page 161: Example Of Servicing Interrupt Requests Generated Simultaneously
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 5-7. Example of Servicing Interrupt Requests Generated Simultaneously Main routine Interrupt request a (level 2) Note 1 Interrupt request b (level 1) Interrupt request b and c are Servicing of interrupt request b • Note 2 Interrupt request c (level 1) acknowledged first according to their... -
Page 162: Interrupt Control Register (Xxicn)
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.3.4 Interrupt control register (xxICn) An interrupt control register is assigned to each maskable interrupt and sets the control conditions for each maskable interrupt request. The interrupt control register can be read/written in 8-bit or 1-bit units. Cautions 1. - Page 163 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION After reset: 47H Address: FFFFF100H to FFFFF156H Symbol <7> <6> xxICn xxIFn xxMKn xxPRn2 xxPRn1 xxPRn0 Note xxIFn Interrupt request flag Interrupt request not generated Interrupt request generated xxMKn Interrupt mask flag Interrupt servicing enabled Interrupt servicing disabled (pending) xxPRn2 xxPRn1...
- Page 164 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION The address and bits of each interrupt control register are as follows. Table 5-2. Interrupt Control Register (xxICn) Address Register <7> <6> FFFFF100H WDTIC WDTIF WDTMK WDTPR2 WDTPR1 WDTPR0 FFFFF102H PIC0 PIF0 PMK0 PPR02 PPR01 PPR00 FFFFF104H PIC1...
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Page 165: In-Service Priority Register (Ispr)
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.3.5 In-service priority register (ISPR) This register holds the priority level of the maskable interrupt currently acknowledged. When an interrupt request is acknowledged, the bit of this register corresponding to the priority level of that interrupt is set to 1 and remains set while the interrupt is serviced. -
Page 166: Watchdog Timer Mode Register (Wdtm)
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.3.7 Watchdog timer mode register (WDTM) This register can be read/written in 8-bit or 1-bit units (for details, refer to CHAPTER 9 WATCHDOG TIMER). After reset: 00H Address: FFFFF384H Symbol <7> WDTM WDTM4 Watchdog timer operation control Count operation stopped Count start after clearing WDTM4... - Page 167 81.3 µ s /512 102.4 µ s 162.7 µ s /1024 Setting prohibited 61 µ s Since sampling is preformed three times, the reliably eliminated noise width is 2 × noise elimination Notes 1. clock. Only in the V850/SB1. User’s Manual U13850EJ6V0UD...
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Page 168: Edge Detection Function
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.3.9 Edge detection function The valid edges of the INTP0 to INTP6 pins can be selected for each pin from the following four types. • Rising edge • Falling edge • Both rising and falling edges •... -
Page 169: Software Exceptions
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.4 Software Exceptions A software exception is generated when the CPU executes the TRAP instruction, and can be always acknowledged. • TRAP instruction format: TRAP vector (where vector is 0 to 1FH) For details of the instruction function, refer to the V850 Series Architecture User’s Manual. 5.4.1 Operation If a software exception occurs, the CPU performs the following processing, and transfers control to the handler routine. -
Page 170: Restore
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.4.2 Restore To restore or return execution from the software exception service routine, the RETI instruction is used. Operation of RETI instruction When the RETI instruction is executed, the CPU performs the following steps, and transfers control to the address of the restored PC. -
Page 171: Ep Flag
5.5 Exception Trap The exception trap is an interrupt that is requested when illegal execution of an instruction takes place. In the V850/SB1 or V850/SB2, an illegal opcode exception (ILGOP: ILeGal OPcode trap) is considered as an exception trap. • Illegal opcode exception: Occurs if the sub opcode field of the instruction to be executed next is not a valid opcode. -
Page 172: Exception Trap Processing
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION How the exception trap is processed is shown below. Figure 5-11. Exception Trap Processing Exception trap (ILGOP) occurs CPU processing EIPC Restored PC EIPSW ECR.EICC Exception code PSW.EP PSW.ID 00000060H Exception processing User’s Manual U13850EJ6V0UD... -
Page 173: Restore
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.5.3 Restore To restore or return execution from the exception trap, the RETI instruction is used. Operation of RETI instruction When the RETI instruction is executed, the CPU performs the following processing, and transfers control to the address of the restored PC. -
Page 174: Priority Control
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.6 Priority Control 5.6.1 Priorities of interrupts and exceptions Table 5-3. Priorities of Interrupts and Exceptions RESET TRAP ILGOP RESET × ← ← ← × ↑ ← ← × ↑ ↑ ← TRAP × ↑ ↑... - Page 175 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION (1) To acknowledge maskable interrupts in service program Service program of maskable interrupt or exception • Save EIPC to memory or register • Save EIPSW to memory or register • EI instruction (enables interrupt acknowledgment) ←...
- Page 176 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION Priorities 0 to 7 (0 is the highest) can be programmed for each maskable interrupt request for multiple interrupt servicing control. To set a priority level, write values to the xxPRn0 to xxPRn2 bits of the interrupt request control register (xxICn) corresponding to each maskable interrupt request.
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Page 177: Interrupt Latency Time
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.7 Interrupt Latency Time The following table describes the interrupt latency time (from interrupt request generation to start of interrupt servicing). Figure 5-13. Pipeline Operation at Interrupt Request Acknowledgment 7 to 14 system clocks 4 system clocks System clock Interrupt request Instruction 1... -
Page 178: Interrupt Request Valid Timing After Ei Instruction
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.8.1 Interrupt request valid timing after EI instruction When an interrupt request signal is generated (IF flag = 1) in the status in which the DI instruction is executed (interrupts disabled) and interrupts are not masked (MK flag = 0), seven system clocks are required from the execution of the EI instruction (interrupts enabled) to the interrupt request acknowledgment by the CPU. -
Page 179: Interrupt Control Register Bit Manipulation Instructions During Dma Transfer
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 5-14. Pipeline Flow and Interrupt Request Signal Generation Timing (a) When DI instruction is executed at eighth clock after EI instruction execution (interrupt request is acknowledged) ei signal intrq signal intrq signal is generated (b) When DI instruction is executed at seventh clock after EI instruction execution (interrupt request is not acknowledged) ei signal... -
Page 180: Key Interrupt Function
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.10 Key Interrupt Function Key interrupts can be generated by inputting a falling edge to the key input pins (KR0 to KR7) by setting the key return mode register (KRM). The key return mode register (KRM) includes 5 bits. The KRM0 bit controls the KR0 to KR3 signals in 4-bit units and the KRM4 to KRM7 bits control corresponding signals from KR4 to KR7 (arbitrary setting from 4 to 8 bits is possible). - Page 181 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 5-15. Key Return Block Diagram INTKR KRM7 KRM6 KRM5 KRM4 KRM0 Key return mode register (KRM) User’s Manual U13850EJ6V0UD...
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Page 182: Chapter 6 Clock Generation Function
(1) Main clock oscillator The oscillator of V850/SB1 has an oscillation frequency of 2 to 20 MHz. The oscillator of the A and B versions of the V850/SB2 has an oscillation frequency of 2 to 12.58 MHz and the oscillator of the H version of the V850/SB2 has an oscillation frequency of 2 to 19 MHz. -
Page 183: Configuration
CHAPTER 6 CLOCK GENERATION FUNCTION 6.2 Configuration Figure 6-1. Clock Generator Clock supplied to Subclock oscillator watch timer, etc. IDLE IDLE control CK2 to CK0 IDLE Main clock Prescaler HALT control oscillator CPU clock HALT Selector STP, control Clock supplied to Prescaler peripheral hardware CLKOUT... -
Page 184: Control Registers
CHAPTER 6 CLOCK GENERATION FUNCTION 6.3.1 Control registers (1) Processor clock control register (PCC) This is a specific register. It can be written to only when a specified combination of sequences is used (see 3.4.9 Specific registers). This register can be read/written in 8-bit or 1-bit units. After reset: Address: FFFFF074H <7>... - Page 185 CHAPTER 6 CLOCK GENERATION FUNCTION (a) Example of main clock operation → → → → subclock operation setup <1> CK2 ← 1: Bit manipulation instructions are recommended. Do not change CK1 and CK0. <2> Subclock operation: The maximum number of the following instructions is required before subclock operation after the CK2 bit is set.
- Page 186 CHAPTER 6 CLOCK GENERATION FUNCTION (2) Power save control register (PSC) This is a specific register. It can be written to only when a specified combination of sequences is used. For details, see 3.4.9 Specific registers. This register can be read/written in 8-bit or 1-bit units. After reset: Address: FFFFF070H <2>...
- Page 187 Clock Note 20 MHz 12.58 MHz 819.2 µ s 1.3 ms 3.3 ms 5.2 ms 6.6 ms 10.4 ms 13.1 ms 20.8 ms 26.2 ms 41.6 ms Other than above Setting prohibited Note Only in the V850/SB1. User’s Manual U13850EJ6V0UD...
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Page 188: Power Save Functions
CHAPTER 6 CLOCK GENERATION FUNCTION 6.4 Power Save Functions 6.4.1 Outline This product provides the following power saving functions. These modes can be combined and switched to suit the target application, which enables effective implementation of low-power systems. (1) HALT mode When in this mode, the clock’s oscillator continues to operate but the CPU’s operating clock is stopped. -
Page 189: Halt Mode
CHAPTER 6 CLOCK GENERATION FUNCTION 6.4.2 HALT mode (1) Settings and operating states In this mode, the clock’s oscillator continues to operate but the CPU’s operating clock is stopped. A clock continues to be supplied for other on-chip peripheral functions to maintain operation of those functions. When HALT mode is set while the CPU is idle, it enables the system’s total power consumption to be reduced. - Page 190 CHAPTER 6 CLOCK GENERATION FUNCTION Table 6-1. Operating Statuses in HALT Mode (1/2) HALT Mode Setting When CPU Operates with Main Clock Item When Subclock Does Not Exist When Subclock Exists Stopped ROM correction Stopped Clock generator Oscillation for main clock and subclock Clock supply to CPU is stopped 16-bit timer (TM0) Operating...
- Page 191 CHAPTER 6 CLOCK GENERATION FUNCTION Table 6-1. Operating Statuses in HALT Mode (2/2) HALT Mode Setting When CPU Operates with Main Clock Item When Subclock Does Not Exist When Subclock Exists Port function Held External bus interface Only bus hold function operates External Operating interrupt...
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Page 192: Idle Mode
CHAPTER 6 CLOCK GENERATION FUNCTION 6.4.3 IDLE mode (1) Settings and operating states This mode stops the entire system except the watch timer by stopping the on-chip main clock supply while the clock oscillator is still operating. Supply to the subclock continues. When this mode is released, there is no need for the oscillator to wait for the oscillation stabilization time, so normal operation can be resumed quickly. - Page 193 CHAPTER 6 CLOCK GENERATION FUNCTION Table 6-2. Operating Statuses in IDLE Mode (2/2) IDLE Mode Settings When Subclock Exists When Subclock Does Not Exist Item External bus interface Stopped External Operating interrupt INTP0 to INTP3 Operating request INTP4 and INTP5 Stopped INTP6 Operates when f is selected for sampling...
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Page 194: Software Stop Mode
CHAPTER 6 CLOCK GENERATION FUNCTION 6.4.4 Software STOP mode (1) Settings and operating states This mode stops the entire system by stopping the main clock oscillator to stop supplying the internal main clock. The subclock oscillator continues operating and the on-chip subclock supply is continued. When the FRC bit in the processor clock control register (PCC) is set to 1, the subclock oscillator’s on-chip feedback resistor is cut. - Page 195 CHAPTER 6 CLOCK GENERATION FUNCTION Table 6-3. Operating Statuses in Software STOP Mode (2/2) Mode Settings When Subclock Exists When Subclock Does Not Exist Item DMA0 to DMA5 Stopped Real-time output Operates when INTTM4 or INTTM5 has been Stopped selected (when TM4 or TM5 is operating) Port function Held External bus interface...
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Page 196: Oscillation Stabilization Time
CHAPTER 6 CLOCK GENERATION FUNCTION 6.5 Oscillation Stabilization Time The following shows the methods for specifying the length of the oscillation stabilization time required to stabilize the oscillator following release of STOP mode. (1) Release by non-maskable interrupt or by unmasked interrupt request STOP mode is released by a non-maskable interrupt or an unmasked interrupt request. -
Page 197: Notes On Power Save Function
CHAPTER 6 CLOCK GENERATION FUNCTION 6.6 Notes on Power Save Function (1) While an instruction is being executed on internal ROM To set the power save mode (IDLE mode or STOP mode) while an instruction is being executed on the internal ROM, insert a NOP instruction as a dummy instruction to correctly execute the routine after releasing the power save mode. - Page 198 (2) While an instruction is being executed on external ROM If the V850/SB1 or V850/SB2 is used under the following conditions, the address indicated by the program counter (PC) differs from the address that actually reads an instruction after the power save mode has been released.
- Page 199 CHAPTER 6 CLOCK GENERATION FUNCTION [Example of prevention program] LDSR rx, 5 ; Sets value of rX to PSW. ST.B r0, PRCMD[r0] ; Writes data to PRCMD. ST.B rD, PSC[r0] ; Sets PSC register. LDSR rY, 5 ; Returns value of PSW. ;...
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Page 200: Chapter 7 Timer/Counter Function
CHAPTER 7 TIMER/COUNTER FUNCTION 7.1 16-Bit Timer (TM0, TM1) 7.1.1 Outline • 16-bit capture/compare registers: 2 (CRn0, CRn1) • Independent capture/trigger inputs: 2 (TIn0, TIn1) • Support of output of capture/match interrupt request signals (INTTMn0, INTTMn1) • Event input (shared with TIn0) via digital noise eliminator and support of edge specification •... - Page 201 CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-1. Block Diagram of TM0 and TM1 Internal bus Capture/compare control register n (CRCn) CRCn2 CRCn1 CRCn0 Selector INTTMn0 16-bit capture/compare Noise Selector TIn1 register n0 (CRn0) eliminator Match Note Count clock Clear 16-bit timer register (TMn) Selector Output controller...
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Page 202: Configuration
CHAPTER 7 TIMER/COUNTER FUNCTION 7.1.3 Configuration Timers 0 and 1 include the following hardware. Table 7-1. Configuration of Timers 0 and 1 Item Configuration 16 bits × 2 (TM0, TM1) Timer registers 16-bit capture/compare registers: 16 bits × 2 each (CRn0, CRn1) Registers Timer outputs 2 (TO0, TO1) - Page 203 CHAPTER 7 TIMER/COUNTER FUNCTION (2) 16-bit capture/compare registers n0 (CR00, CR10) CRn0 is a 16-bit register that functions as a capture register and as a compare register. Whether this register functions as a capture or compare register is specified by using the CRCn0 bit of the CRCn register. (a) When using CRn0 as compare register The value set to CRn0 is always compared with the count value of the TMn register.
- Page 204 CHAPTER 7 TIMER/COUNTER FUNCTION (3) 16-bit capture/compare register n1 (CR01, CR11) This is a 16-bit register that can be used as a capture register and a compare register. Whether it is used as a capture register or compare register is specified by the CRCn2 bit of the CRCn register. (a) When using CRn1 as compare register The value set to CRn1 is always compared with the count value of TMn.
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Page 205: Timer 0, 1 Control Registers
CHAPTER 7 TIMER/COUNTER FUNCTION 7.1.4 Timer 0, 1 control registers The registers to control timers 0 and 1 are shown below. • 16-bit timer mode control register n (TMCn) • Capture/compare control register n (CRCn) • 16-bit timer output control register n (TOCn) •... - Page 206 CHAPTER 7 TIMER/COUNTER FUNCTION After reset: 00H Address: FFFFF208H, FFFFF218H <0> TMCn TMCn3 TMCn2 TMCn1 OVFn (n = 0, 1) TMCn3 TMCn2 TMCn1 Operation mode and TOn output timing Generation of interrupt clear mode selector selector Operation stops (TMn is Not affected Not generated cleared to 0)
- Page 207 CHAPTER 7 TIMER/COUNTER FUNCTION (2) Capture/compare control registers 0, 1 (CRC0, CRC1) CRCn controls the operation of 16-bit capture/compare register n (CRn0 and CRn1). CRCn is set by an 8-bit or 1-bit memory manipulation instruction. RESET input clears CRC0 and CRC1 to 00H. After reset: 00H R/W Address: FFFFF20AH, FFFFF21AH CRCn...
- Page 208 CHAPTER 7 TIMER/COUNTER FUNCTION (3) 16-bit timer output control registers 0, 1 (TOC0, TOC1) TOCn controls the operation of the timer n output controller by setting or resetting the R-S flip-flop (LV0), enabling or disabling reverse output, enabling or disabling output of timer n, enabling or disabling one-shot pulse output operation, and selecting the output trigger for the one-shot pulse by software.
- Page 209 Notes 1. The external clock requires a pulse longer than twice that of the internal clock (f /2). 2. Only in the V850/SB1. Cautions 1. When selecting the valid edge of TI00 as the count clock, do not specify the clear & start mode entered on the valid edge of TI00 or TI00 as a capture trigger.
- Page 210 Notes 1. The external clock requires a pulse longer than twice that of the internal clock (f /2). 2. Only in the V850/SB1. Cautions 1. When selecting the valid edge of TI10 as the count clock, do not specify the clear & start mode entered on the valid edge of TI10 or TI10 as a capture trigger.
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Page 211: 16-Bit Timer Operation
CHAPTER 7 TIMER/COUNTER FUNCTION 7.2 16-Bit Timer Operation 7.2.1 Operation as interval timer (16 bits) TMn operates as an interval timer when 16-bit timer mode control register n (TMCn) and capture/compare control register n (CRCn) are set as shown in Figure 7-2 (n = 0, 1). In this case, TMn repeatedly generates an interrupt at the time interval specified by the count value set in advance to 16-bit capture/compare register n0 (CRn0). - Page 212 CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-3. Configuration of Interval Timer 16-bit capture/compare register n0 (CRn0) INTTMn0 Note Count clock Selector 16-bit timer register n (TMn) OVFn Noise TIn0 eliminator Clear circuit Note The count clock is set by the PRMn0 and PRMn1 registers. Remarks 1.
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Page 213: Ppg Output Operation
CHAPTER 7 TIMER/COUNTER FUNCTION 7.2.2 PPG output operation TMn can be used for PPG (Programmable Pulse Generator) output by setting 16-bit timer mode control register n (TMCn) and capture/compare control register n (CRCn) as shown in Figure 7-5. The PPG output function outputs a square wave from the TOn pin with a cycle specified by the count value set in advance to 16-bit capture/compare register n0 (CRn0) and a pulse width specified by the count value set in advance to 16-bit capture/compare register n1 (CRn1). - Page 214 CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-6. Configuration of PPG Output 16-bit capture/compare register n0 (CRn0) Clear Note Count clock 16-bit timer register n (TMn) circuit Noise TIn0 eliminator 16-bit capture/compare register n1 (CRn1) Note The count clock is set by the PRMn0 and PRMn1 registers. Remarks 1.
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Page 215: Pulse Width Measurement
CHAPTER 7 TIMER/COUNTER FUNCTION 7.2.3 Pulse width measurement 16-bit timer register n (TMn) can be used to measure the pulse widths of the signals input to the TIn0 and TIn1 pins. Measurement can be carried out with TMn used as a free-running counter or by restarting the timer in synchronization with the edge of the signal input to the TIn0 pin. - Page 216 CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-9. Configuration for Pulse Width Measurement with Free-Running Counter Note Count clock OVFn Selector 16-bit timer register n (TMn) 16-bit capture/compare register n1 TIn0 (CRn1) INTTMn1 Internal bus Note The count clock is set by the PRMn0 and PRMn1 registers. Remarks 1.
- Page 217 CHAPTER 7 TIMER/COUNTER FUNCTION (2) Measurement of two pulse widths with free-running counter The pulse widths of the two signals respectively input to the TIn0 and TIn1 pins can be measured when 16-bit timer register n (TMn) is used as a free-running counter (refer to Figure 7-11). When the edge specified by the ESn00 and ESn01 bits of prescaler mode register n0 (PRMn0) is input to the TIn0 pin, the value of the TMn is loaded to 16-bit capture/compare register n1 (CRn1) and an external interrupt request signal (INTTMn1) is set.
- Page 218 CHAPTER 7 TIMER/COUNTER FUNCTION • Capture operation (free-running mode) The following figure illustrates the operation of the capture register when the capture trigger is input. Figure 7-12. CRn1 Capture Operation with Rising Edge Specified Count clock N − 3 N − 2 N −...
- Page 219 CHAPTER 7 TIMER/COUNTER FUNCTION (3) Pulse width measurement with free-running counter and two capture registers When 16-bit timer register n (TMn) is used as a free-running counter (refer to Figure 7-14), the pulse width of the signal input to the TIn0 pin can be measured. When the edge specified by the ESn00 and ESn01 bits of prescaler mode register n0 (PRMn0) is input to the TIn0 pin, the value of TMn is loaded to 16-bit capture/compare register n1 (CRn1), and an external interrupt request signal (INTTMn1) is set.
- Page 220 CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-15. Timing of Pulse Width Measurement with Free-Running Counter and Two Capture Registers (with Rising Edge Specified) Count clock TMn count 0000H 0001H D0 + 1 D1 + 1 FFFFH 0000H D2 + 1 value TIn0 pin input Value loaded to CRn1...
- Page 221 CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-16. Control Register Settings for Pulse Width Measurement by Restarting (a) 16-bit timer mode control registers 0, 1 (TMC0, TMC1) TMCn3 TMCn2 TMCn1 OVFn TMCn Clears and starts at valid edge of TIn0 pin. (b) Capture/compare control registers 0, 1 (CRC0, CRC1) CRCn2 CRCn1 CRCn0...
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Page 222: Operation As External Event Counter
CHAPTER 7 TIMER/COUNTER FUNCTION 7.2.4 Operation as external event counter TMn can be used as an external event counter that counts the number of clock pulses input to the TIn0 pin from an external source by using 16-bit timer register n (TMn). Each time the valid edge specified by prescaler mode register n0 (PRMn0) has been input, TMn is incremented. -
Page 223: Operation To Output Square Wave
CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-19. Configuration of External Event Counter 16-bit capture/compare register n (CRn0) Match INTTMn0 Clear Note Count clock Selector OVFn 16-bit timer/counter n (TMn) Noise eliminator 16-bit capture/compare Valid edge of TIn0 register n1 (CRn1) Internal bus Note The count clock is set by the PRMn0 and PRMn1 registers. - Page 224 CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-21. Control Register Settings in Square Wave Output Mode (a) 16-bit timer mode control registers 0, 1 (TMC0, TMC1) TMCn3 TMCn2 TMCn1 OVFn TMCn Clears and starts on match between TMn and CRn0. (b) Capture/compare control registers 0, 1 (CRC0, CRC1) CRCn2 CRCn1 CRCn0...
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Page 225: Operation To Output One-Shot Pulse
CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-22. Timing of Square Wave Output Operation Count clock N − 1 N − 1 TMn count value 0001H 0000H 0001H 0002H 0000H 0000H 0002H CRn0 INTTMn0 TOn pin output Remark n = 0, 1 7.2.6 Operation to output one-shot pulse TMn can output a one-shot pulse in synchronization with a software trigger and an external trigger (TIn0 pin input). - Page 226 CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-23. Control Register Settings for One-Shot Pulse Output with Software Trigger (a) 16-bit timer mode control registers 0, 1 (TMC0, TMC1) TMCn3 TMCn2 TMCn1 OVFn TMCn Free-running mode (b) Capture/compare control registers 0, 1 (CRC0, CRC1) CRCn2 CRCn1 CRCn0...
- Page 227 CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-24. Timing of One-Shot Pulse Output Operation with Software Trigger Sets 0CH to TMCn (TMn count starts) Count clock TMn count N − 1 M − 1 0000H 0001H N + 1 0000H M + 1 M + 2 value CRn1 set...
- Page 228 CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-25. Control Register Settings for One-Shot Pulse Output with External Trigger (a) 16-bit timer mode control registers 0, 1 (TMC0, TMC1) TMCn3 TMCn2 TMCn1 OVFn TMCn Clears and starts at valid edge of TIn0 pin. (b) Capture/compare control registers 0, 1 (CRC0, CRC1) CRCn2 CRCn1...
- Page 229 CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-26. Timing of One-Shot Pulse Output Operation with External Trigger (with Rising Edge Specified) Sets 08H to TMCn (TMn count starts) Count clock TMn count M − 2 M − 1 0000H 0001H 0000H N + 1 N + 2 M + 1 M + 2...
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Page 230: Cautions
CHAPTER 7 TIMER/COUNTER FUNCTION 7.2.7 Cautions (1) Error on starting timer An error of up to 1 clock occurs before the match signal is generated after the timer has been started. This is because 16-bit timer register n (TMn) is started asynchronously to the count pulse. Figure 7-27. - Page 231 CHAPTER 7 TIMER/COUNTER FUNCTION (4) Data hold timing of capture register If the valid edge is input to the TIn0 pin while 16-bit capture/compare register n1 (CRn1) is being read, CRn1 performs the capture operation, but this read value is not guaranteed. However, the interrupt request signal (INTTMn1) is set as a result of detection of the valid edge.
- Page 232 CHAPTER 7 TIMER/COUNTER FUNCTION (7) Operation of OVFn bit (a) OVFn bit set The OVFn bit is set to 1 in the following case in addition to when the TMn register overflows: Select the mode in which the timer is cleared and started on a match between TMn and CRn0 or the mode in which it is cleared and started by the valid edge of TIn0.
- Page 233 CHAPTER 7 TIMER/COUNTER FUNCTION (c) One-shot pulse output The one-shot pulse output operates correctly only in free-running mode or in clear & start mode at the valid edge of the TIn0 pin. The one-shot pulse cannot be output in the clear & start mode on a match of TMn and CRn0 because an overflow does not occur.
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Page 234: 8-Bit Timer (Tm2 To Tm7)
CHAPTER 7 TIMER/COUNTER FUNCTION 7.3 8-Bit Timer (TM2 to TM7) 7.3.1 Outline • 8-bit compare registers: 8 (CRn0) Can be used as 16-bit compare registers by connecting in cascade (2 max.). • Compare match/overflow interrupt request signal (INTTMn) output enabled •... -
Page 235: Configuration
CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-31. Block Diagram of TM2 to TM7 Internal bus 8-bit compare Selector INTTMn register n (CRn0) Mask Match circuit Note 2 8-bit counter n Selector Selector Note 1 (TMn) Count clock Clear Invert level Selector TCEn TMCn6 TMCn4 LVSm LVRm TMCm1 TOEm... -
Page 236: Timer N Control Register
CHAPTER 7 TIMER/COUNTER FUNCTION (1) 8-bit counters 2 to 7 (TM2 to TM7) TMn is an 8-bit read-only register that counts the count pulses. The counter is incremented in synchronization with the rising edge of the count clock. TM2 and TM3 or TM5 and TM6 can be connected in cascade and used as 16-bit timers. When TMm and TMm+1 are connected in cascade and used as a 16-bit timer, they can be read by a 16-bit memory manipulation instruction. - Page 237 − Setting prohibited Note Only in the V850/SB1. Cautions 1. When TCLn0 and TCLn1 are overwritten by different data, write after temporarily stopping the timer. 2. Always set bits 3 to 7 to in TCLn0 to 0, and bits 1 to 7 in TCLn1 to 0.
- Page 238 − Setting prohibited Note Only in the V850/SB1. Cautions 1. When TCLn0 and TCLn1 are overwritten by different data, write after temporarily stopping the timer. 2. Always set bits 3 to 7 of TCLn0 and bits 1 to 7 of TCLn1 to 0.
- Page 239 − TM0 overflow signal Note Only in the V850/SB1. Cautions 1. When TCLn0 and TCLn1 are overwritten by different data, write after temporarily stopping the timer. 2. Always set bits 3 to 7 of TCLn0 and bits 1 to 7 of TCLn1 to 0.
- Page 240 CHAPTER 7 TIMER/COUNTER FUNCTION (2) 8-bit timer mode control registers 2 to 7 (TMC2 to TMC7) The TMCn register makes the following six settings. (1) Controls counting by 8-bit counter n (TMn) (2) Selects the operating mode of 8-bit counter n (TMn) (3) Selects the individual mode or cascade connection mode (4) Sets the state of the timer output flip-flop (5) Controls the timer flip-flop or selects the active level in the PWM (free-running) mode...
- Page 241 CHAPTER 7 TIMER/COUNTER FUNCTION After reset: Address: TMC2 FFFFF246H TMC5 FFFFF276H TMC3 FFFFF256H TMC6 FFFFF286H TMC4 FFFFF266H TMC7 FFFFF296H <7> <3> <2> <0> TMCn TMCn6 TCEn TMCn4 LVSm LVRm TMCm1 TOEm (n = 2 to 7, m = 2 to 5) TCEn TMn count operation control Counting is disabled after the counter is cleared to 0 (prescaler disabled)
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Page 242: 8-Bit Timer Operation
CHAPTER 7 TIMER/COUNTER FUNCTION 7.4 8-Bit Timer Operation 7.4.1 Operation as interval timer (8-bit operation) The timer operates as an interval timer that repeatedly generates interrupts at the interval of the count preset by 8- bit compare register n (CRn0). If the count in 8-bit counter n (TMn) matches the value set in CRn0, the value of TMn is cleared to 0 and TMn continues counting. - Page 243 CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-32. Timing of Interval Timer Operation (2/3) When CRn0 = 00H Count clock TMn 00H CRn0 TCEn INTTMn Interval time Remark n = 2 to 7, m = 2 to 5 When CRn0 = FFH Count clock CRn0 TCEn...
- Page 244 CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-32. Timing of Interval Timer Operation (3/3) Operated by CRn0 transition (M < N) Count clock CRn0 TCEn INTTMn CRn0 transition TMn overflows since M < N Remark n = 2 to 7, m = 2 to 5 Operated by CRn0 transition (M >...
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Page 245: Operation As External Event Counter
CHAPTER 7 TIMER/COUNTER FUNCTION 7.4.2 Operation as external event counter The external event counter counts the number of external clock pulses that are input to TIn. Each time a valid edge specified by timer clock selection register n0, n1 (TCLn0, TCLn1) is input, TMn is incremented. -
Page 246: Operation As Square Wave Output (8-Bit Resolution)
CHAPTER 7 TIMER/COUNTER FUNCTION 7.4.3 Operation as square wave output (8-bit resolution) A square wave with any frequency is output at the interval preset by 8-bit compare register n (CRn0). By setting bit 0 (TOEn) of 8-bit timer mode control register n (TMCn) to 1, the output state of TOn is inverted with the count preset in CRn0 as the interval. -
Page 247: Operation As 8-Bit Pwm Output
CHAPTER 7 TIMER/COUNTER FUNCTION 7.4.4 Operation as 8-bit PWM output By setting the TMCn6 bit of 8-bit timer mode control register n (TMCn) to 1, the timer operates as a PWM output. Pulses with the duty factor determined by the value set to 8-bit compare register n (CRn0) are output from TOn. Set the width of the active level of the PWM pulse to CRn0. -
Page 248: Timing Of Pwm Output
CHAPTER 7 TIMER/COUNTER FUNCTION Basic operation of PWM output Figure 7-35. Timing of PWM Output Basic operation (active level = H) Count clock N + 1 CRn0 TCEn INTTMn Active level Inactive level Active level When CRn0 = 00H Count clock 00H 01H N + 1 N + 2 CRn0... -
Page 249: Timing Of Operation Based On Crn0 Transitions
CHAPTER 7 TIMER/COUNTER FUNCTION Operation based on CRn0 transitions Figure 7-36. Timing of Operation Based on CRn0 Transitions When the CRn0 value changes from N to M before TMn overflows Count clock N + 1 N + 2 M + 1 M + 2 M + 1 M + 2... -
Page 250: Operation As Interval Timer (16 Bits)
TIMER/COUNTER FUNCTION 7.4.5 Operation as interval timer (16 bits) (1) Cascade connection (16-bit timer) mode The V850/SB1 and V850/SB2 provide 16-bit registers that can be used only when connected in cascade. The following registers are available. TM2, TM3 cascade connection:... -
Page 251: Cascade Connection Mode With 16-Bit Resolution
CHAPTER 7 TIMER/COUNTER FUNCTION A timing example of the cascade connection mode with 16-bit resolution is shown below. Figure 7-37. Cascade Connection Mode with 16-Bit Resolution Count clock N + 1 TMn + 1 − CRn0 CR(n+1)0 TCEn TCEn + 1 INTTMn Interval time Enable operation starting count... -
Page 252: Cautions
CHAPTER 7 TIMER/COUNTER FUNCTION 7.4.6 Cautions (1) Error when the timer starts An error of up to 1 clock occurs in the time until the match signal is generated after the timer starts. The reason is that 8-bit counter n (TMn) starts asynchronous to the count pulse. Figure 7-38. -
Page 253: Chapter 8 Watch Timer
(WTNHC) register (WTNCS) (WTNM) Internal bus µ µ µ µ Caution The WTNHC register is available only in the B versions of the V850/SB1, PD703036H, 703036HY, 703037H, 703037HY, 70F3036H, 70F3036HY, 70F3037H, and 70F3037HY. Remark : Main clock frequency : Subclock frequency Watch timer clock frequency User’s Manual U13850EJ6V0UD... -
Page 254: Configuration
Watch timer high-speed clock selection register (WTNHC) Watch timer clock selection register (WTNCS) µ Note The WTNHC register is available only in the B versions of the V850/SB1, PD703036H, 703036HY, 703037H, 703037HY, 70F3036H, 70F3036HY, 70F3037H, and 70F3037HY. User’s Manual U13850EJ6V0UD... -
Page 255: Watch Timer Control Registers
(WTNCS) control the watch timer. The watch timer should be operated after setting the count clock and interval time. µ µ µ µ Caution The WTNHC register is available only in the B versions of the V850/SB1, PD703036H, 703036HY, 703037H, 703037HY, 70F3036H, 70F3036HY, 70F3037H, and 70F3037HY. - Page 256 RESET input clears WTNHC to 00H. After reset: 00H Address: FFFFF366H WTNHC WTNCS2 µ Caution The WTNHC register is available only in the B versions of the V850/SB1, PD703036H, 703036HY, 703037H, 703037HY, 70F3036H, 70F3036HY, 70F3037H, and 70F3037HY. User’s Manual U13850EJ6V0UD...
- Page 257 Other than above Setting prohibited – µ Note The WTNCS2 bit is available only in the B versions of the V850/SB1, PD703036H, 703036HY, 703037H, 703037HY, 70F3036H, 70F3036HY, 70F3037H, and 70F3037HY. Remark WTNM7 is bit 7 of the WTNM register. User’s Manual U13850EJ6V0UD...
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Page 258: Operation
CHAPTER 8 WATCH TIMER 8.4 Operation 8.4.1 Operation as watch timer The watch timer operates at time intervals of 0.5 seconds with the subclock (32.768 kHz). The watch timer generates an interrupt request at fixed time intervals. The count operation of the watch timer is started when bits 0 (WTNM0) and 1 (WTNM1) of the watch timer mode control register (WTNM) are set to 1. -
Page 259: Cautions
CHAPTER 8 WATCH TIMER Figure 8-2. Operation Timing of Watch Timer/Interval Timer 5-bit counter Overflow Overflow Start Count clock f Watch timer interrupt INTWTN Interrupt time of watch timer (0.5 s) Interrupt time of watch timer (0.5 s) Interval timer interrupt INTWTNI Interval time Interval time... -
Page 260: Chapter 9 Watchdog Timer
CHAPTER 9 WATCHDOG TIMER 9.1 Functions The watchdog timer has the following functions. • Watchdog timer • Interval timer • Selecting the oscillation stabilization time Caution Use the watchdog timer mode register (WDTM) to select the watchdog timer mode or the interval timer mode. - Page 261 26.2 ms 41.6 ms 52.4 ms 83.3 ms 209.7 ms 333.4 ms Note Only in the V850/SB1. (2) Interval timer mode Interrupts are generated at a preset time interval. Table 9-2. Interval Time of Interval Timer Clock Interval Time Note = 20 MHz = 12.58 MHz...
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Page 262: Configuration
20 MHz 12.58 MHz 819.2 µ s 1.3 ms 3.3 ms 5.2 ms 6.6 ms 10.4 ms 13.1 ms 20.8 ms (after reset) 26.2 ms 41.6 ms Other than above Setting prohibited Note Only in the V850/SB1. User’s Manual U13850EJ6V0UD... - Page 263 5.2 ms 6.6 ms 10.4 ms 13.1 ms 20.8 ms 41.6 ms 26.2 ms 83.3 ms 52.4 ms 209.7 ms 333.4 ms Note Only in the V850/SB1. Caution Be sure to set bits 3 to 7 to 0. User’s Manual U13850EJ6V0UD...
- Page 264 CHAPTER 9 WATCHDOG TIMER (3) Watchdog timer mode register (WDTM) This register sets the operating mode of the watchdog timer, and enables and disables counting. WDTM is set by an 8-bit or 1-bit memory manipulation instruction. RESET input clears WDTM to 00H. After reset: 00H Address: FFFFF384H <7>...
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Page 265: Operation
819.2 µ s 1.3 ms 1.6 ms 2.6 ms 3.3 ms 5.2 ms 6.6 ms 10.4 ms 13.1 ms 20.8 ms 26.2 ms 41.6 ms 52.4 ms 83.3 ms 209.7 ms 333.4 ms Note Only in the V850/SB1. User’s Manual U13850EJ6V0UD... -
Page 266: Operation As Interval Timer
819.2 µ s 1.3 ms 1.6 ms 2.6 ms 3.3 ms 5.2 ms 6.6 ms 10.4 ms 13.1 ms 20.8 ms 26.2 ms 41.6 ms 52.4 ms 83.3 ms 209.7 ms 333.4 ms Note Only in the V850/SB1. User’s Manual U13850EJ6V0UD... -
Page 267: Standby Function Control Register
Other than above Setting prohibited Note Only in the V850/SB1. Caution The wait time at the release of the STOP mode does not include the time (“a” in the figure below) until clock oscillation starts after releasing the STOP mode when RESET is input or an interrupt is generated. -
Page 268: Chapter 10 Serial Interface Function
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.1 Overview The V850/SB1 and V850/SB2 incorporate the following serial interfaces. Note • Channel 0: 3-wire serial I/O (CSI0)/I • Channel 1: 3-wire serial I/O (CSI1)/Asynchronous serial interface (UART0) Note • Channel 2: 3-wire serial I/O (CSI2)/I •... -
Page 269: Configuration
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.2.1 Configuration CSIn includes the following hardware. Table 10-1. Configuration of CSIn Item Configuration Registers Serial I/O shift registers 0 to 3 (SIO0 to SIO3) Control registers Serial operation mode registers 0 to 3 (CSIM0 to CSIM3) Serial clock selection registers 0 to 3 (CSIS0 to CSIS3) Figure 10-1. -
Page 270: Csin Control Registers
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.2.2 CSIn control registers CSIn is controlled by the following registers. • Serial operation mode register n (CSIMn) • Serial clock selection register n (CSISn) (1) Serial clock selection registers 0 to 3 (CSIS0 to CSIS3) and serial operation mode registers 0 to 3 (CSIM0 to CSIM3) The CSISn register is used to set serial interface channel n’s serial clock. - Page 271 CHAPTER 10 SERIAL INTERFACE FUNCTION After reset : 00H Address: CSIS0 FFFFF2A4H CSIS2 FFFFF2C4H CSIS1 FFFFF2B4H CSIS3 FFFFF2D4H CSISn SCLn2 (n = 0 to 3) After reset: Address: CSIM0 FFFFF2A2H CSIM2 FFFFF2C2H CSIM1 FFFFF2B2H CSIM3 FFFFF2D2H <7> CSIMn CSIEn MODEn SCLn1 SCLn0 (n = 0 to 3)
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Page 272: Operations
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.2.3 Operations CSIn has the following two operation modes. • Operation stop mode • 3-wire serial I/O mode (1) Operation stop mode Serial transfers are not performed in this mode, enabling a reduction in power consumption. In operation stop mode, if SIn, SOn, and SCKn pin are also used as I/O ports, they can be used as normal I/O ports as well. -
Page 273: Csimn Setting (3-Wire Serial I/O Mode)
CHAPTER 10 SERIAL INTERFACE FUNCTION (2) 3-wire serial I/O mode 3-wire serial I/O mode is useful when connecting to a peripheral I/O device that includes a clocked serial interface, a display controller, etc. This mode executes data transfers via three lines: a serial clock line (SCKn), serial output line (SOn), and serial input line (SIn). -
Page 274: Timing Of 3-Wire Serial I/O Mode
CHAPTER 10 SERIAL INTERFACE FUNCTION (b) Communication operations In 3-wire serial I/O mode, data is transmitted and received in 8-bit units. Each bit of data is sent or received in synchronization with the serial clock. Serial I/O shift register n (SIOn) is shifted in synchronization with the falling edge of the serial clock. Transmission data is held in the SOn latch and is output from the SOn pin. -
Page 275: I C Bus (A Versions)
C bus function, set the P10/SDA0, P12/SCL0, P20/SDA1, and P22/SCL1 pins to N-ch open drain output. The products with an on-chip I C bus are shown below. • V850/SB1: µ PD703031AY, 703032AY, 703033AY, 70F3032AY, 70F3033AY • V850/SB2: µ PD703034AY, 703035AY, 703037AY, 70F3035AY, 70F3037AY The I C0 and I C1 have the following two modes. -
Page 276: Block Diagram Of I 2 C
CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-5. Block Diagram of I Internal bus IIC status register n (IICSn) MSTSn ALDn EXCn COIn TRCn ACKDn STDn SPDn IIC control register n (IICCn) Slave address register n (SVAn) IICEn LRELn WRELn SPIEn WTIMn ACKEn STTn SPTn SDAn Match... -
Page 277: C Bus
CHAPTER 10 SERIAL INTERFACE FUNCTION A serial bus configuration example is shown below. Figure 10-6. Serial Bus Configuration Example Using I C Bus Master CPU1 Master CPU2 Serial data bus Slave CPU2 Slave CPU1 Serial clock Address 1 Address 2 Slave CPU3 Address 3 Slave IC... -
Page 278: Configuration
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3.1 Configuration Cn includes the following hardware (n = 0, 1). Table 10-2. Configuration of I Item Configuration Registers IIC shift registers 0 and 1 (IIC0, IIC1) Slave address registers 0 and 1 (SVA0, SVA1) Control registers IIC control registers 0 and 1 (IICC0, IICC1) IIC status registers 0 and 1 (IICS0, IICS1) - Page 279 CHAPTER 10 SERIAL INTERFACE FUNCTION (7) Interrupt request signal generator This circuit controls the generation of interrupt request signals (INTIICn). An I C interrupt is generated following either of two triggers. • Eighth or ninth clock of the serial clock (set by WTIMn bit) •...
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Page 280: C Control Registers
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3.2 I C control registers C0 and I C1 are controlled by the following registers. • IIC control registers 0, 1 (IICC0, IICC1) • IIC status registers 0, 1 (IICS0, IICS1) • IIC clock selection registers 0, 1 (IICCL0, IICCL1) •... - Page 281 CHAPTER 10 SERIAL INTERFACE FUNCTION (1/4) After reset: 00H Address: FFFFF340H, FFFFF350H <7> <6> <5> <4> <3> <2> <1> <0> IICCn IICEn LRELn WRELn SPIEn WTIMn ACKEn STTn SPTn (n = 0, 1) IICEn Cn operation enable/disable specification Operation stopped. IIC status register n (IICSn) preset. Internal operation stopped. Enables operation.
- Page 282 CHAPTER 10 SERIAL INTERFACE FUNCTION (2/4) WRELn Wait cancellation control Do not cancel wait Cancel wait. This setting is automatically cleared after wait is canceled. Note Condition for clearing (WRELn = 0) Condition for setting (WRELn = 1) • Automatically cleared after execution •...
- Page 283 CHAPTER 10 SERIAL INTERFACE FUNCTION (3/4) ACKEn Acknowledge control Disable acknowledgment. Enable acknowledgment. During the ninth clock period, the SDA line is set to low level. However, the ACK is invalid during address transfers and is valid when EXCn = 1. Note Condition for clearing (ACKEn = 0) Condition for setting (ACKEn = 1)
- Page 284 CHAPTER 10 SERIAL INTERFACE FUNCTION (4/4) SPTn Stop condition trigger Stop condition is not generated. Stop condition is generated (termination of master device’s transfer). After the SDAn line goes to low level, either set the SCLn line to high level or wait until it goes to high level.
- Page 285 CHAPTER 10 SERIAL INTERFACE FUNCTION (2) IIC status registers 0, 1 (IICS0, IICS1) IICSn indicates the status of the I Cn bus. IICSn can be set by an 8-bit or 1-bit memory manipulation instruction. IICSn is a read-only register (n = 0, 1). RESET input sets IICSn to 00H.
- Page 286 CHAPTER 10 SERIAL INTERFACE FUNCTION (2/3) EXCn Detection of extension code reception Extension code was not received. Extension code was received. Condition for clearing (EXCn = 0) Condition for setting (EXCn = 1) • When a start condition is detected •...
- Page 287 CHAPTER 10 SERIAL INTERFACE FUNCTION (3/3) ACKDn Detection of ACK ACK was not detected. ACK was detected. Condition for clearing (ACKDn = 0) Condition for setting (ACKD = 1) • When a stop condition is detected • After the SDAn line is set to low level at the rising edge •...
- Page 288 CHAPTER 10 SERIAL INTERFACE FUNCTION (3) IIC clock selection registers 0, 1 (IICCL0, IICCL1) IICCLn is used to set the transfer clock for the I Cn bus. IICCLn can be set by an 8-bit or 1-bit memory manipulation instruction. Bits SMCn, CLn1 and CLn0 are set using the CLXn bit of IIC function expansion register n (IICXn) in combination with bits IICCEn1 and IICCEn0 of IIC clock expansion register n (IICCEn) (n = 0, 1) (see 10.3.2 (6) I Cn transfer clock setting method).
- Page 289 CHAPTER 10 SERIAL INTERFACE FUNCTION (4) IIC function expansion registers 0, 1 (IICX0, IICX1) These registers set the function expansion of I Cn (valid only in high-speed mode). IICXn is set with a 1-bit or 8-bit memory manipulation instruction. Set the CLXn bit in combination with the SMCn, DFCn, CLn1, and the CLn0 bits of IIC clock selection register n (IICCLn) and the IICCEn1 and IICCEn0 bits of IIC clock expansion register n (IICCEn) (see 10.3.2 (6) I Cn transfer clock setting method) (n = 0, 1).
- Page 290 TM3 output/66 Other than above Setting prohibited Note Only in the V850/SB1 and the H versions of the V850/SB2. Remarks 1. n = 0, 1 2. x: don’t care 3. When the output of the timer is selected as the clock, it is not necessary to set the P26/TO2/TI2 and P27/TO3/TI3 pins in the timer output mode.
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Page 291: I 2 C Bus Mode Functions
CHAPTER 10 SERIAL INTERFACE FUNCTION (7) IIC shift registers 0, 1 (IIC0, IIC1) IICn is used for serial transmission/reception (shift operations) that is synchronized with the serial clock. It can be read from or written to in 8-bit units, but data should not be written to IICn during a data transfer (n = 0, 1). After reset: 00H Address: FFFFF348H, FFFFF358H <0>... -
Page 292: I C Bus Definitions And Control Methods
CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-7. Pin Configuration Diagram Slave device Master device Clock output (Clock output) (Clock input) Clock input Data output Data output Data input Data input 10.3.4 I C bus definitions and control methods The following section describes the I C bus’s serial data communication format and the signals used by the I bus. -
Page 293: Start Condition
CHAPTER 10 SERIAL INTERFACE FUNCTION Start condition The start condition is met when the SCLn pin is at high level and the SDAn pin changes from high level to low level. The start conditions for the SCLn pin and SDAn pin are signals that the master device outputs to the slave device when starting a serial transfer. -
Page 294: Transfer Direction Specification
CHAPTER 10 SERIAL INTERFACE FUNCTION The slave address and the eighth bit, which specifies the transfer direction as described in (3) Transfer direction specification below, are written together to the IIC shift register (IICn) and are then output. Received addresses are written to IICn (n = 0, 1). The slave address is assigned to the higher 7 bits of IICn. -
Page 295: Ack Signal
CHAPTER 10 SERIAL INTERFACE FUNCTION Acknowledge signal (ACK) The acknowledge signal (ACK) is used by the transmitting and receiving devices to confirm serial data reception. The receiving device returns one ACK signal for every 8 bits of data it receives. The transmitting device normally receives an ACK signal after transmitting 8 bits of data. -
Page 296: Stop Condition
CHAPTER 10 SERIAL INTERFACE FUNCTION Stop condition When the SCLn pin is at high level, changing the SDAn pin from low level to high level generates a stop condition (n = 0, 1). A stop condition is a signal that the master device outputs to the slave device when serial transfer has been completed. -
Page 297: Wait Signal
CHAPTER 10 SERIAL INTERFACE FUNCTION Wait signal (WAIT) The wait signal (WAIT) is used to notify the communication partner that a device (master or slave) is preparing to transmit or receive data (i.e., is in a wait state). Setting the SCLn pin to low level notifies the communication partner of the wait status. When the wait status has been canceled for both the master and slave devices, the next data transfer can begin (n = 0, 1). - Page 298 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-14. Wait Signal (2/2) (b) When master and slave devices both have a nine-clock wait (master: transmission, slave: reception, and ACKEn = 1) Master and slave both wait Master after output of ninth clock IIC0 data write (cancel wait) IIC0 Slave...
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Page 299: I 2 C Interrupt Requests (Intiicn)
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3.5 I C interrupt requests (INTIICn) The following shows the value of IIC status register n (IICSn) at the INTIICn interrupt request generation timing and at the INTIICn interrupt timing (n = 0, 1). (1) Master device operation (a) Start ~ Address ~ Data ~ Data ~ Stop (normal transmission/reception) <1>... - Page 300 CHAPTER 10 SERIAL INTERFACE FUNCTION (b) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (restart) <1> When WTIMn = 0 STTn = 1 SPTn = 1 ↓ ↓ AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 ∆7 L1: IICSn = 10XXX110B...
- Page 301 CHAPTER 10 SERIAL INTERFACE FUNCTION (c) Start ~ Code ~ Data ~ Data ~ Stop (extension code transmission) <1> When WTIMn = 0 SPTn = 1 ↓ AD6 to AD0 D7 to D0 D7 to D0 ∆5 L1: IICSn = 1010X110B L2: IICSn = 1010X000B L3: IICSn = 1010X000B (WTIMn = 1) L4: IICSn = 1010XX00B...
- Page 302 CHAPTER 10 SERIAL INTERFACE FUNCTION (2) Slave device operation (when receiving slave address data (match with SVAn)) (a) Start ~ Address ~ Data ~ Data ~ Stop <1> When WTIMn = 0 AD6 to AD0 D7 to D0 D7 to D0 ∆4 L1: IICSn = 0001X110B L2: IICSn = 0001X000B...
- Page 303 CHAPTER 10 SERIAL INTERFACE FUNCTION (b) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn = 0 (after restart, match with SVAn) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 ∆5 L1: IICSn = 0001X110B L2: IICSn = 0001X000B...
- Page 304 CHAPTER 10 SERIAL INTERFACE FUNCTION (c) Start ~ Address ~ Data ~ Start ~ Code ~ Data ~ Stop <1> When WTIMn = 0 (after restart, extension code reception) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 ∆5 L1: IICSn = 0001X110B L2: IICSn = 0001X000B...
- Page 305 CHAPTER 10 SERIAL INTERFACE FUNCTION (d) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn = 0 (after restart, mismatch with address (= not extension code)) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 ∆4 L1: IICSn = 0001X110B...
- Page 306 CHAPTER 10 SERIAL INTERFACE FUNCTION (3) Slave device operation (when receiving extension code) (a) Start ~ Code ~ Data ~ Data ~ Stop <1> When WTIMn = 0 AD6 to AD0 D7 to D0 D7 to D0 ∆4 L1: IICSn = 0010X010B L2: IICSn = 0010X000B L3: IICSn = 0010X000B ∆...
- Page 307 CHAPTER 10 SERIAL INTERFACE FUNCTION (b) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn = 0 (after restart, match with SVAn) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 ∆5 L1: IICSn = 0010X010B L2: IICSn = 0010X000B...
- Page 308 CHAPTER 10 SERIAL INTERFACE FUNCTION (c) Start ~ Code ~ Data ~ Start ~ Code ~ Data ~ Stop <1> When WTIMn = 0 (after restart, extension code reception) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 ∆5 L1: IICSn = 0010X010B L2: IICSn = 0010X000B...
- Page 309 CHAPTER 10 SERIAL INTERFACE FUNCTION (d) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn = 0 (after restart, mismatch with address (= not extension code)) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 ∆4 L1: IICSn = 0010X010B...
- Page 310 CHAPTER 10 SERIAL INTERFACE FUNCTION (4) Operation without communication (a) Start ~ Code ~ Data ~ Data ~ Stop AD6 to AD0 D7 to D0 D7 to D0 ∆1 ∆ 1: IICSn = 00000001B ∆: Generated only when SPIEn = 1 Remark n = 0, 1 (5) Arbitration loss operation (operation as slave after arbitration loss)
- Page 311 CHAPTER 10 SERIAL INTERFACE FUNCTION (b) When arbitration loss occurs during transmission of extension code <1> When WTIMn = 0 AD6 to AD0 D7 to D0 D7 to D0 ∆4 L1: IICSn = 0110X010B (Example: when ALDn is read during interrupt servicing) L2: IICSn = 0010X000B L3: IICSn = 0010X000B ∆...
- Page 312 CHAPTER 10 SERIAL INTERFACE FUNCTION (6) Operation when arbitration loss occurs (no communication after arbitration loss) (a) When arbitration loss occurs during transmission of slave address data AD6 to AD0 D7 to D0 D7 to D0 ∆2 L1: IICSn = 01000110B (Example: when ALDn is read during interrupt servicing) ∆...
- Page 313 CHAPTER 10 SERIAL INTERFACE FUNCTION (c) When arbitration loss occurs during data transfer <1> When WTIMn = 0 AD6 to AD0 D7 to D0 D7 to D0 ∆3 L1: IICSn = 10001110B L2: IICSn = 01000000B (Example: when ALDn is read during interrupt servicing) ∆...
- Page 314 CHAPTER 10 SERIAL INTERFACE FUNCTION (d) When loss occurs due to restart condition during data transfer <1> Not extension code (Example: mismatches with SVAn) AD6 to AD0 D7 to Dn AD6 to AD0 D7 to D0 ∆3 L1: IICSn = 1000X110B L2: IICSn = 01000110B (Example: when ALDn is read during interrupt servicing) ∆...
- Page 315 CHAPTER 10 SERIAL INTERFACE FUNCTION (e) When loss occurs due to stop condition during data transfer AD6 to AD0 D7 to Dn ∆2 L1: IICSn = 1000X110B ∆ 2: IICSn = 01000001B L: Always generated Remark ∆: Generated only when SPIEn = 1 X: don’t care Dn = D6 to D0 n = 0, 1...
- Page 316 CHAPTER 10 SERIAL INTERFACE FUNCTION (g) When arbitration loss occurs due to a stop condition when attempting to generate a restart condition When WTIMn = 1 STTn = 1 ↓ AD6 to AD0 D7 to D0 ∆3 L1: IICSn = 1000X110B L2: IICSn = 1000XX00B ∆...
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Page 317: Interrupt Request (Intiicn) Generation Timing And Wait Control
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3.6 Interrupt request (INTIICn) generation timing and wait control The setting of bit 3 (WTIMn) of IIC control register n (IICCn) determines the timing by which INTIICn is generated and the corresponding wait control, as shown below (n = 0, 1). Table 10-4. -
Page 318: Address Match Detection Method
CHAPTER 10 SERIAL INTERFACE FUNCTION Stop condition detection INTIICn is generated when a stop condition is detected. Remark n = 0, 1 10.3.7 Address match detection method In I C bus mode, the master device can select a particular slave device by transmitting the corresponding slave address. -
Page 319: Arbitration
CHAPTER 10 SERIAL INTERFACE FUNCTION Table 10-5. Extension Code Bit Definitions Slave Address R/W Bit Description 0000 General call address 0000 Start byte 0000 CBUS address 0000 Address that is reserved for a different bus format 1111 10-bit slave address specification 10.3.10 Arbitration When several master devices simultaneously output a start condition (when STTn is set to 1 before STDn is set to Note... -
Page 320: Wakeup Function
CHAPTER 10 SERIAL INTERFACE FUNCTION Table 10-6. Status During Arbitration and Interrupt Request Generation Timing Status During Arbitration Interrupt Request Generation Timing Note 1 At falling edge of eighth or ninth clock following byte transfer During address transmission Read/write data after address transmission During extension code transmission Read/write data after extension code transmission During data transmission... -
Page 321: Communication Reservation
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3.12 Communication reservation To start master device communications when not currently using the bus, a communication reservation can be made to enable transmission of a start condition when the bus is released. There are two modes under which the bus is not used. -
Page 322: Communication Reservation Timing
CHAPTER 10 SERIAL INTERFACE FUNCTION The communication reservation timing is shown below. Figure 10-16. Communication Reservation Timing Write to Program processing IIC0 Set SPD Communication Hardware processing reservation and INTIIC0 Output by master with bus mastership IICn: IIC shift register n STTn: Bit 1 of IIC control register n (IICCn) STDn:... -
Page 323: Communication Reservation Flowchart
CHAPTER 10 SERIAL INTERFACE FUNCTION The communication reservation flowchart is illustrated below. Figure 10-18. Communication Reservation Flowchart SET1 STTn ; Sets STT flag (communication reservation). Define communication ; Defines that communication reservation is in effect (defines and sets user flag to any part of RAM). reservation ;... -
Page 324: Cautions
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3.13 Cautions After a reset, when changing from a mode in which no stop condition has been detected (the bus has not been released) to a master device communication mode, first generate a stop condition to release the bus, then perform master device communication. -
Page 325: Communication Operations
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3.14 Communication operations Master operations The following is a flowchart of the master operations. Figure 10-19. Master Operation Flowchart START ← ××H IICCLn Select transfer clock. ← ××H IICCn IICEn = SPIEn = WTIMn = 1 INTIICn = 1? Start IICn write transfer. -
Page 326: Slave Operation Flowchart
CHAPTER 10 SERIAL INTERFACE FUNCTION Slave operation An example of slave operation is shown below. Figure 10-20. Slave Operation Flowchart START ← ××H IICCn IICEn = 1 INTIICn = 1? EXCn = 1? Communicate? COIn = 1? LRELn = 1 No (receive) TRCn = 1? Yes (transmit) -
Page 327: Timing Of Data Communication
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3.15 Timing of data communication When using I C bus mode, the master device outputs an address via the serial bus to select one of several slave devices as its communication partner. After outputting the slave address, the master device transmits the TRCn bit (bit 3 of IIC status register n (IICSn)) that specifies the data transfer direction and then starts serial communication with the slave device. -
Page 328: (When 9-Clock Wait Is Selected For Both Master And Slave) (1/3
CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-21. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (1/3) (a) Start condition ~ address Processing by master device ← ← IICn IICn address IICn data ACKDn STDn SPDn... - Page 329 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-21. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (2/3) (b) Data Processing by master device ← ← IICn data IICn data IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn...
- Page 330 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-21. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (3/3) (c) Stop condition Processing by master device ← ← IICn IICn data IICn address ACKDn STDn SPDn WTIMn ACKEn...
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Page 331: (When 9-Clock Wait Is Selected For Both Master And Slave) (1/3
CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-22. Example of Slave to Master Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (1/3) (a) Start condition ~ address Processing by master device ← ← IICn IICn address IICn FFH Note ACKDn STDn SPDn... - Page 332 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-22. Example of Slave to Master Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (2/3) (b) Data Processing by master device IICn ← FFH Note IICn ← FFH Note IICn ACKDn STDn SPDn WTIMn...
- Page 333 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-22. Example of Slave to Master Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (3/3) (c) Stop condition Processing by master device ← ← IICn IICn FFH Note IICn address ACKDn STDn SPDn WTIMn...
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Page 334: I C Bus (B And H Versions)
C bus function, set the P10/SDA0, P12/SCL0, P20/SDA1, and P22/SCL1 pins to N-ch open drain output. The products with an on-chip I C bus are shown below. • V850/SB1: µ PD703030BY, 703031BY, 703032BY, 703033BY, 70F3030BY, 70F3032BY, 70F3033BY • V850/SB2: µ PD703034BY, 703035BY, 703036HY, 703037HY, 70F3035BY, 70F3036HY, 70F3037HY The I C0 and I C1 have the following two modes. -
Page 335: Block Diagram Of I 2 C
CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-23. Block Diagram of I Internal bus IIC status register n (IICSn) MSTSn ALDn EXCn COIn TRCn ACKDn STDn SPDn IIC control register n (IICCn) IICEn LRELn WRELn SPIEn WTIMn ACKEn STTn SPTn Start Slave address Clear condition... -
Page 336: Serial Bus Configuration Example Using I
CHAPTER 10 SERIAL INTERFACE FUNCTION A serial bus configuration example is shown below. Figure 10-24. Serial Bus Configuration Example Using I C Bus Master CPU1 Master CPU2 Serial data bus Slave CPU2 Slave CPU1 Serial clock Address 1 Address 2 Slave CPU3 Address 3 Slave IC... -
Page 337: Configuration
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.4.1 Configuration Cn includes the following hardware (n = 0, 1). Table 10-8. Configuration of I Item Configuration Registers IIC shift registers 0 and 1 (IIC0, IIC1) Slave address registers 0 and 1 (SVA0, SVA1) Control registers IIC control registers 0 and 1 (IICC0, IICC1) IIC status registers 0 and 1 (IICS0, IICS1) - Page 338 CHAPTER 10 SERIAL INTERFACE FUNCTION (7) Interrupt request signal generator This circuit controls the generation of interrupt request signals (INTIICn). An I C interrupt is generated following either of two triggers. • Eighth or ninth clock of the serial clock (set by WTIMn bit) •...
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Page 339: C Control Register
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.4.2 I C control register C0 and I C1 are controlled by the following registers. • IIC control registers 0, 1 (IICC0, IICC1) • IIC status registers 0, 1 (IICS0, IICS1) • IIC flag registers 0, 1 (IICF0, IICF1) •... - Page 340 CHAPTER 10 SERIAL INTERFACE FUNCTION (1/4) After reset: 00H Address: FFFFF340H, FFFFF350H <7> <6> <5> <4> <3> <2> <1> <0> IICCn IICEn LRELn WRELn SPIEn WTIMn ACKEn STTn SPTn (n = 0, 1) IICEn Cn operation enable/disable specification Stops operation. Presets IIC status register n (IICSn). Stops internal operation. Enables operation.
- Page 341 CHAPTER 10 SERIAL INTERFACE FUNCTION (2/4) WRELn Wait cancellation control Does not cancel wait Cancels wait. This setting is automatically cleared after wait is canceled. Note Condition for clearing (WRELn = 0) Condition for setting (WRELn = 1) • Automatically cleared after execution •...
- Page 342 CHAPTER 10 SERIAL INTERFACE FUNCTION (3/4) ACKEn Acknowledge control Disable acknowledge. Enable acknowledge. During the ninth clock period, the SDA line is set to low level. However, the ACK is invalid during address transfers and is valid when EXCn = 1. Note Condition for clearing (ACKEn = 0) Condition for setting (ACKEn = 1)
- Page 343 CHAPTER 10 SERIAL INTERFACE FUNCTION (4/4) SPTn Stop condition trigger Stop condition is not generated. Stop condition is generated (termination of master device’s transfer). After the SDAn line goes to low level, either set the SCLn line to high level or wait until it goes to high level.
- Page 344 CHAPTER 10 SERIAL INTERFACE FUNCTION (2) IIC status registers 0, 1 (IICS0, IICS1) IICSn indicates the status of the I Cn bus. IICSn can be set by an 8-bit or 1-bit memory manipulation instruction. IICSn is a read-only register (n = 0, 1). RESET input sets IICSn to 00H.
- Page 345 CHAPTER 10 SERIAL INTERFACE FUNCTION (2/3) EXCn Detection of extension code reception Extension code was not received. Extension code was received. Condition for clearing (EXCn = 0) Condition for setting (EXCn = 1) • When a start condition is detected •...
- Page 346 CHAPTER 10 SERIAL INTERFACE FUNCTION (3/3) ACKDn Detection of ACK ACK was not detected. ACK was detected. Condition for clearing (ACKDn = 0) Condition for setting (ACKD = 1) • When a stop condition is detected • After the SDAn line is set to low level at the rising edge •...
- Page 347 CHAPTER 10 SERIAL INTERFACE FUNCTION (3) IIC flag registers 0, 1 (IICF0, IICF1) IICFn is used to set the I Cn operation mode and to indicate the I C bus status. IICFn can be set by an 8-bit or 1-bit memory manipulation instruction. The IICRSVn bit is used to enable/disable the communication reservation function (see 10.4.12 Communication reservation).
- Page 348 CHAPTER 10 SERIAL INTERFACE FUNCTION (2/2) STCENn Initial start enable trigger After operation is enabled (IICEn = 1), cannot generate a start condition until a stop condition is detected. After operation is enabled (IICEn = 1), can generates a start condition without detecting a stop condition. Condition for clearing (STCENn = 0) Condition for setting (STCENn = 1) •...
- Page 349 CHAPTER 10 SERIAL INTERFACE FUNCTION (4) IIC clock selection registers 0, 1 (IICCL0, IICCL1) IICCLn is used to set the transfer clock for the I Cn bus. IICCLn can be set by an 8-bit or 1-bit memory manipulation instruction. Bits SMCn, CLn1 and CLn0 are set using CLXn bit of IIC function expansion register n (IICXn) in combination with bits IICCEn1 and IICCEn0 of IIC clock expansion register n (IICCEn) (n = 0, 1) (see 10.4.2 (7) I Cn transfer clock setting method).
- Page 350 CHAPTER 10 SERIAL INTERFACE FUNCTION (5) IIC function expansion registers 0, 1 (IICX0, IICX1) These registers set the function expansion of I Cn (valid only in high-speed mode). IICXn is set by an 8-bit or 1-bit memory manipulation instruction. Set the CLXn bit in combination with the SMCn, DFCn, CLn1, and the CLn0 bits of IIC clock selection register n (IICCLn) and the IICCEn1 and IICCEn0 bits of IIC clock expansion register n (IICCEn) (see 10.4.2 (7) I Cn transfer clock setting method) (n = 0, 1).
- Page 351 CHAPTER 10 SERIAL INTERFACE FUNCTION m x T + t m/2 x T m/2 x T SCLn SCLn inversion SCLn inversion SCLn inversion The selection clock is set using a combination of the SMCn, CLn1, and CLn0 bits of IIC clock selection register n (IICCLn), the CLXn bit of IIC function expansion register n (IICXn), and IICCEn1 and the IICCEn0 bits of IIC clock expansion register n (IICCEn) (n = 0, 1).
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Page 352: I 2 C Bus Mode Functions
CHAPTER 10 SERIAL INTERFACE FUNCTION (8) IIC shift registers 0, 1 (IIC0, IIC1) IICn is used for serial transmission/reception (shift operations) that is synchronized with the serial clock. It can be read from or written to in 8-bit units, but data should not be written to IICn during a data transfer (n = 0, 1). After reset: 00H Address: FFFFF348H, FFFFF358H <0>... -
Page 353: I C Bus Definitions And Control Methods
CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-25. Pin Configuration Diagram Slave device Master device Clock output (Clock output) (Clock input) Clock input Data output Data output Data input Data input 10.4.4 I C bus definitions and control methods The following section describes the I C bus’s serial data communication format and the signals used by the I bus. -
Page 354: Start Conditions
CHAPTER 10 SERIAL INTERFACE FUNCTION Start condition A start condition is met when the SCLn pin is at high level and the SDAn pin changes from high level to low level. The start conditions for the SCLn pin and SDAn pin are signals that the master device outputs to the slave device when starting a serial transfer. -
Page 355: Transfer Direction Specification
CHAPTER 10 SERIAL INTERFACE FUNCTION The slave address and the eighth bit, which specifies the transfer direction as described in (3) Transfer direction specification below, are together written to the IIC shift register (IICn) and are then output. Received addresses are written to IICn (n = 0, 1). The slave address is assigned to the higher 7 bits of IICn. -
Page 356: Ack Signal
CHAPTER 10 SERIAL INTERFACE FUNCTION Acknowledge signal (ACK) The acknowledge signal (ACK) is used by the transmitting and receiving devices to confirm serial data reception. The receiving device returns one ACK signal for each 8 bits of data it receives. The transmitting device normally receives an ACK signal after transmitting 8 bits of data. -
Page 357: Stop Condition
CHAPTER 10 SERIAL INTERFACE FUNCTION When the local address is received, an ACK signal is automatically output in synchronization with the falling edge of the SCLn’s eighth clock regardless of the ACKEn value. No ACK signal is output if the received address is not a local address (n = 0, 1). -
Page 358: Wait Signal
CHAPTER 10 SERIAL INTERFACE FUNCTION Wait signal (WAIT) The wait signal (WAIT) is used to notify the communication partner that a device (master or slave) is preparing to transmit or receive data (i.e., is in a wait state). Setting the SCLn pin to low level notifies the communication partner of the wait status. When wait status has been canceled for both the master and slave devices, the next data transfer can begin (n = 0, 1). - Page 359 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-32. Wait Signal (2/2) (b) When master and slave devices both have a nine-clock wait (master: transmission, slave: reception, and ACKEn = 1) Master and slave both wait Master after output of ninth clock. IIC0 data write (cancel wait) IIC0 Slave...
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Page 360: C Interrupt Requests (Intiicn)
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.4.5 I C interrupt requests (INTIICn) The following shows the value of IIC status register n (IICSn) at the INTIICn interrupt request generation timing and at the INTIICn interrupt timing (n = 0, 1). (1) Master device operation (a) Start ~ Address ~ Data ~ Data ~ Stop (normal transmission/reception) <1>... - Page 361 CHAPTER 10 SERIAL INTERFACE FUNCTION (b) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (restart) <1> When WTIMn = 0 STTn = 1 SPTn = 1 ↓ ↓ AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 ∆7 L1: IICSn = 10XXX110B...
- Page 362 CHAPTER 10 SERIAL INTERFACE FUNCTION (c) Start ~ Code ~ Data ~ Data ~ Stop (extension code transmission) <1> When WTIMn = 0 SPTn = 1 ↓ AD6 to AD0 D7 to D0 D7 to D0 ∆5 L1: IICSn = 1010X110B L2: IICSn = 1010X000B L3: IICSn = 1010X000B (WTIMn = 1) L4: IICSn = 1010XX00B...
- Page 363 CHAPTER 10 SERIAL INTERFACE FUNCTION (2) Slave device operation (when receiving slave address data (match with SVAn)) (a) Start ~ Address ~ Data ~ Data ~ Stop <1> When WTIMn = 0 AD6 to AD0 D7 to D0 D7 to D0 ∆4 L1: IICSn = 0001X110B L2: IICSn = 0001X000B...
- Page 364 CHAPTER 10 SERIAL INTERFACE FUNCTION (b) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn = 0 (after restart, match with SVAn) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 ∆5 L1: IICSn = 0001X110B L2: IICSn = 0001X000B...
- Page 365 CHAPTER 10 SERIAL INTERFACE FUNCTION (c) Start ~ Address ~ Data ~ Start ~ Code ~ Data ~ Stop <1> When WTIMn = 0 (after restart, extension code reception) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 ∆5 L1: IICSn = 0001X110B L2: IICSn = 0001X000B...
- Page 366 CHAPTER 10 SERIAL INTERFACE FUNCTION (d) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn = 0 (after restart, mismatch with address (= not extension code)) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 ∆4 L1: IICSn = 0001X110B...
- Page 367 CHAPTER 10 SERIAL INTERFACE FUNCTION (3) Slave device operation (when receiving extension code) (a) Start ~ Code ~ Data ~ Data ~ Stop <1> When WTIMn = 0 AD6 to AD0 D7 to D0 D7 to D0 ∆4 L1: IICSn = 0010X010B L2: IICSn = 0010X000B L3: IICSn = 0010X000B ∆...
- Page 368 CHAPTER 10 SERIAL INTERFACE FUNCTION (b) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn = 0 (after restart, match with SVAn) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 ∆5 L1: IICSn = 0010X010B L2: IICSn = 0010X000B...
- Page 369 CHAPTER 10 SERIAL INTERFACE FUNCTION (c) Start ~ Code ~ Data ~ Start ~ Code ~ Data ~ Stop <1> When WTIMn = 0 (after restart, extension code reception) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 ∆5 L1: IICSn = 0010X010B L2: IICSn = 0010X000B...
- Page 370 CHAPTER 10 SERIAL INTERFACE FUNCTION (d) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn = 0 (after restart, mismatch with address (= not extension code)) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 ∆4 L1: IICSn = 0010X010B...
- Page 371 CHAPTER 10 SERIAL INTERFACE FUNCTION (4) Operation without communication (a) Start ~ Code ~ Data ~ Data ~ Stop AD6 to AD0 D7 to D0 D7 to D0 ∆1 ∆ 1: IICSn = 00000001B ∆: Generated only when SPIEn = 1 Remark n = 0, 1 (5) Arbitration loss operation (operation as slave after arbitration loss)
- Page 372 CHAPTER 10 SERIAL INTERFACE FUNCTION (b) When arbitration loss occurs during transmission of extension code <1> When WTIMn = 0 AD6 to AD0 D7 to D0 D7 to D0 ∆4 L1: IICSn = 0110X010B (Example: when ALDn is read during interrupt servicing) L2: IICSn = 0010X000B L3: IICSn = 0010X000B ∆...
- Page 373 CHAPTER 10 SERIAL INTERFACE FUNCTION (6) Operation when arbitration loss occurs (no communication after arbitration loss) (a) When arbitration loss occurs during transmission of slave address data AD6 to AD0 D7 to D0 D7 to D0 ∆2 L1: IICSn = 01000110B (Example: when ALDn is read during interrupt servicing) ∆...
- Page 374 CHAPTER 10 SERIAL INTERFACE FUNCTION (c) When arbitration loss occurs during data transfer <1> When WTIMn = 0 AD6 to AD0 D7 to D0 D7 to D0 ∆3 L1: IICSn = 10001110B L2: IICSn = 01000000B (Example: when ALDn is read during interrupt servicing) ∆...
- Page 375 CHAPTER 10 SERIAL INTERFACE FUNCTION (d) When loss occurs due to restart condition during data transfer <1> Not extension code (Example: mismatches with SVAn) AD6 to AD0 D7 to Dn AD6 to AD0 D7 to D0 ∆3 L1: IICSn = 1000X110B L2: IICSn = 01000110B (Example: when ALDn is read during interrupt servicing) ∆...
- Page 376 CHAPTER 10 SERIAL INTERFACE FUNCTION (e) When loss occurs due to stop condition during data transfer AD6 to AD0 D7 to Dn ∆2 L1: IICSn = 1000X110B ∆ 2: IICSn = 01000001B L: Always generated Remark ∆: Generated only when SPIEn = 1 X: don’t care Dn = D6 to D0 n = 0, 1...
- Page 377 CHAPTER 10 SERIAL INTERFACE FUNCTION (g) When arbitration loss occurs due to a stop condition when attempting to generate a restart condition When WTIMn = 1 STTn = 1 ↓ AD6 to AD0 D7 to D0 ∆3 L1: IICSn = 1000X110B L2: IICSn = 1000XX00B ∆...
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Page 378: Interrupt Request (Intiicn) Generation Timing And Wait Control
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.4.6 Interrupt request (INTIICn) generation timing and wait control The setting of bit 3 (WTIMn) in IIC control register n (IICCn) determines the timing by which INTIICn is generated and the corresponding wait control, as shown below (n = 0, 1). Table 10-10. -
Page 379: Address Match Detection Method
CHAPTER 10 SERIAL INTERFACE FUNCTION Stop condition detection INTIICn is generated when a stop condition is detected. Remark n = 0, 1 10.4.7 Address match detection method When in I C bus mode, the master device can select a particular slave device by transmitting the corresponding slave address. -
Page 380: Arbitration
CHAPTER 10 SERIAL INTERFACE FUNCTION Table 10-11. Extension Code Bit Definitions Slave Address R/W Bit Description 0000 General call address 0000 Start byte 0000 CBUS address 0000 Address that is reserved for different bus format 1111 10-bit slave address specification 10.4.10 Arbitration When several master devices simultaneously output a start condition (when STTn is set to 1 before STDn is set to Note... -
Page 381: Arbitration Timing Example
CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-33. Arbitration Timing Example Master 1 Hi-Z Hi-Z Master 1 loses arbitration Master 2 Transfer lines Remark n = 0, 1 Table 10-12. Status During Arbitration and Interrupt Request Generation Timing Status During Arbitration Interrupt Request Generation Timing Note 1 At falling edge of eighth or ninth clock following byte transfer... -
Page 382: Wakeup Function
CHAPTER 10 SERIAL INTERFACE FUNCTION Notes 1. When WTIMn (bit 3 of the IIC control register n (IICCn)) = 1, an interrupt request occurs at the falling edge of the ninth clock. When WTIMn = 0 and the extension code’s slave address is received, an interrupt request occurs at the falling edge of the eighth clock (n = 0, 1). -
Page 383: Communication Reservation
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.4.12 Communication reservation (1) When communication reservation function is enabled (IICRSVn of IICFn register = 0) To start master device communications when not currently using a bus, a communication reservation can be made to enable transmission of a start condition when the bus is released. There are two modes under which the bus is not used. -
Page 384: Communication Reservation Timing
CHAPTER 10 SERIAL INTERFACE FUNCTION The communication reservation timing is shown below. Figure 10-34. Communication Reservation Timing Write to Program processing IIC0 Set SPD Communication Hardware processing reservation and INTIIC0 Output by master with bus access IICn: IIC shift register n STTn: Bit 1 of IIC control register n (IICCn) STDn:... -
Page 385: Communication Reservation Flowchart
CHAPTER 10 SERIAL INTERFACE FUNCTION The communication reservation flowchart is illustrated below. Figure 10-36. Communication Reservation Flowchart SET1 STTn Sets STT bit (communication reservation). Define communication Defines that communication reservation is in effect reservation (defines and sets user flag to any part of RAM). Secures wait period set by software (see Table 10-13). -
Page 386: Timing At Which Sttn = 1 Cannot Be Set
CHAPTER 10 SERIAL INTERFACE FUNCTION (2) When communication reservation function is disabled (IICRSVn of IICFn register = 1) If the STTn bit of the IICn register is set when the bus is not participating in the current communication while bus communication is in progress, this request is rejected and a start condition is not generated. -
Page 387: Master Communication Start Or Stop Flowchart
CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-38. Master Communication Start or Stop Flowchart IICBSYn = 0 ? Sets STTn bit SET1 STTn Secures wait period by software Wait (see Table 10-14) STCFn = 0 ? communication status Master IICn ← XXH IICn write operation communication stop Remark... -
Page 388: Cautions
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.4.13 Cautions (a) When STCENn of IICFn register = 0 Immediately after the I C operation is enabled, the communication status (IICBSYn of IICFn register = 1) is recognized regardless of the actual bus status. To perform master communication in the status in which the stop condition is not detected, first generate a stop condition to release the bus and then perform master communication. -
Page 389: Communication Operations
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.4.14 Communication operations (1) Master operations The following shows an example of the master communication flowchart when the communication reservation function is enabled (IICRSVn = 0) and when communication is started after a stop condition is detected (STCENn = 0). -
Page 390: Master Operation Flowchart (2)
CHAPTER 10 SERIAL INTERFACE FUNCTION (2) Master operation The following shows an example of the master communication flowchart when the communication reservation function is disabled (IICRSVn = 1) and when communication is started without detecting a stop condition (STCENn = 1). Figure 10-40. -
Page 391: Slave Operation Flowchart
CHAPTER 10 SERIAL INTERFACE FUNCTION (3) Slave operation The following shows an example of the slave communication flowchart. Figure 10-41. Slave Operation Flowchart START IICCn ← XXH IICEn = 1 INTIICn = 1? EXCn = 1? participates in communication? COIn = 1? LRELn = 1 No (receive) TRCn = 1? -
Page 392: Timing Of Data Communication
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.4.15 Timing of data communication When using I C bus mode, the master device outputs an address via the serial bus to select one of several slave devices as its communication partner. After outputting the slave address, the master device transmits the TRCn bit (bit 3 of IIC status register n (IICSn)) that specifies the data transfer direction and then starts serial communication with the slave device. -
Page 393: (When 9-Clock Wait Is Selected For Both Master And Slave) (1/3
CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-42. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (1/3) (a) Start condition ~ address Processing by master device ← ← IICn IICn address IICn data ACKDn STDn SPDn... - Page 394 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-42. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (2/3) (b) Data Processing by master device ← ← IICn data IICn data IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn...
- Page 395 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-42. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (3/3) (c) Stop condition Processing by master device ← ← IICn IICn data IICn address ACKDn STDn SPDn WTIMn ACKEn...
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Page 396: (When 9-Clock Wait Is Selected For Both Master And Slave) (1/3
CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-43. Example of Slave to Master Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (1/3) (a) Start condition ~ address Processing by master device ← ← IICn IICn address IICn FFH Note ACKDn STDn SPDn... - Page 397 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-43. Example of Slave to Master Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (2/3) (b) Data Processing by master device IICn ← FFH Note IICn ← FFH Note IICn ACKDn STDn SPDn WTIMn...
- Page 398 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-43. Example of Slave to Master Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (3/3) (c) Stop condition Processing by master device ← ← IICn IICn FFH Note IICn address ACKDn STDn SPDn WTIMn...
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Page 399: Asynchronous Serial Interface (Uart0, Uart1)
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.5 Asynchronous Serial Interface (UART0, UART1) UARTn (n = 0, 1) has the following two operation modes. (1) Operation stop mode This mode is used when serial transfers are not performed. It can therefore be used to reduce power consumption. -
Page 400: Block Diagram Of Uartn
CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-44. Block Diagram of UARTn Internal bus Receive buffer registers 0, 1 (RXB0, RXB1) Receive shift registers RXD0, RXD1 0, 1 (RX0, RX1) Transmit shift registers TXD0, TXD1 0, 1 (TXS0, TXS1) Receive control INTSR0, parity check INTSR1... -
Page 401: Uartn Control Registers
CHAPTER 10 SERIAL INTERFACE FUNCTION (4) Transmission controller The transmission controller controls transmit operations, such as adding a start bit, parity bit, and stop bit to data that is written to transmit shift register n (TXSn), based on the values set to asynchronous serial interface mode register n (ASIMn). - Page 402 CHAPTER 10 SERIAL INTERFACE FUNCTION (1) Asynchronous serial interface mode registers 0, 1 (ASIM0, ASIM1) ASIMn is an 8-bit register that controls the serial transfer operations of UARTn. ASIMn can be set by an 8-bit or 1-bit memory manipulation instruction. RESET input clears these registers to 00H.
- Page 403 CHAPTER 10 SERIAL INTERFACE FUNCTION (2) Asynchronous serial interface status registers 0, 1 (ASIS0, ASIS1) When a receive error occurs in asynchronous serial interface mode, these registers indicate the type of error. ASISn can be read using an 8-bit or 1-bit memory manipulation instruction. RESET input clears these registers to 00H.
- Page 404 CHAPTER 10 SERIAL INTERFACE FUNCTION (3) Baud rate generator control registers 0, 1 (BRGC0, BRGC1) These registers set the serial clock for UARTn. BRGCn can be set by an 8-bit memory manipulation instruction. RESET input clears these registers to 00H. After reset: 00H Address: FFFFF304H, FFFFF314H BRGCn...
- Page 405 CHAPTER 10 SERIAL INTERFACE FUNCTION (4) Baud rate generator mode control registers n0, n1 (BRGMCn0, BRGMCn1) These registers set the UARTn source clock. BRGMCn0 and BRGMCn1 are set by an 8-bit memory manipulation instruction. RESET input clears these registers to 00H. After reset: 00H Address: FFFFF30EH, FFFFF31EH BRGMCn0...
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Page 406: Operations
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.5.3 Operations UARTn has the following two operation modes. • Operation stop mode • Asynchronous serial interface mode (1) Operation stop mode In this mode serial transfers are not performed, allowing a reduction in power consumption. When in operation stop mode, pins can be used as normal ports. -
Page 407: Asimn Setting (Asynchronous Serial Interface Mode)
CHAPTER 10 SERIAL INTERFACE FUNCTION (2) Asynchronous serial interface mode This mode enables full-duplex operation, in which one byte of data is transmitted and received after the start bit. The on-chip dedicated UARTn baud rate generator enables communications using a wide range of selectable baud rates. -
Page 408: Asisn Setting (Asynchronous Serial Interface Mode)
CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-47. ASISn Setting (Asynchronous Serial Interface Mode) After reset: 00H Address: FFFFF302H, FFFFF312H ASISn OVEn (n = 0, 1) Parity error flag No parity error Parity error (Transmit data parity does not match) Framing error flag No framing error Note 1 Framing error... -
Page 409: Brgcn Setting (Asynchronous Serial Interface Mode)
CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-48. BRGCn Setting (Asynchronous Serial Interface Mode) After reset: 00H Address: FFFFF304H, FFFFF314H BRGCn MDLn7 MDLn6 MDLn5 MDLn4 MDLn3 MDLn2 MDLn1 MDLn0 (n = 0, 1) Input clock selection × × × − Setting prohibited •... -
Page 410: Brgmcn0 And Brgmcn1 Settings (Asynchronous Serial Interface Mode)
CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-49. BRGMCn0 and BRGMCn1 Settings (Asynchronous Serial Interface Mode) After reset: 00H Address: FFFFF30EH, FFFFF31EH BRGMCn0 TPSn2 TPSn1 TPSn0 (n = 0, 1) After reset: 00H Address: FFFFF320H, FFFFF322H BRGMCn1 TPSn3 (n = 0, 1) TPSn3 TPSn2 TPSn1... - Page 411 –0.16 0.63 –0.50 300000 2.56 –0.16 –1.24 1.01 312500 –1.54 0.64 –1.54 0.00 Notes 1. Only in the V850/SB1 and the H versions of the V850/SB2 2. Only in the V850/SB1 Remark : Main clock oscillation frequency User’s Manual U13850EJ6V0UD...
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Page 412: Error Tolerance (When K = 16), Including Sampling Errors
CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-50. Error Tolerance (When k = 16), Including Sampling Errors Ideal sampling point 256T 288T 320T 352T 304T 336T Basic timing START STOP (clock cycle T) 15.5T High-speed clock (clock cycle T’) START STOP enabling normal Sampling error reception... -
Page 413: Format Of Transmit/Receive Data In Asynchronous Serial Interface
CHAPTER 10 SERIAL INTERFACE FUNCTION (3) Communication operations (a) Data format As shown in Figure 10-43, the format of the transmit/receive data consists of a start bit, character bits, a parity bit, and one or more stop bits. Asynchronous serial interface mode register n (ASIMn) is used to set the character bit length, parity selection, and stop bit length within each data frame (n = 0, 1). - Page 414 CHAPTER 10 SERIAL INTERFACE FUNCTION (b) Parity types and operations The parity bit is used to detect bit errors in transfer data. Usually, the same type of parity bit is used by the transmitting and receiving sides. When odd parity or even parity is set, errors in the parity bit (the odd- number bit) can be detected.
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Page 415: Timing Of Asynchronous Serial Interface Transmit Completion Interrupt
CHAPTER 10 SERIAL INTERFACE FUNCTION (c) Transmission The transmit operation is started when transmit data is written to transmit shift register n (TXSn). A start bit, parity bit, and stop bit(s) are automatically added to the data. Starting the transmit operation shifts out the data in TXSn, thereby emptying TXSn, after which a transmit completion interrupt (INTSTn) is issued. -
Page 416: Timing Of Asynchronous Serial Interface Receive Completion Interrupt
CHAPTER 10 SERIAL INTERFACE FUNCTION (d) Reception The receive operation is enabled when “1” is set to bit 6 (RXEn) of asynchronous serial interface mode register n (ASIMn), and the input via the RXDn pin is sampled. The serial clock specified by BRGCn is used when sampling the RXDn pin. When the RXDn pin goes low, the 8-bit counter begins counting and the start timing signal for data sampling is output when half of the specified baud rate time has elapsed. -
Page 417: Receive Error Timing
CHAPTER 10 SERIAL INTERFACE FUNCTION (e) Receive error Three types of errors can occur during a receive operation: a parity error, framing error, and overrun error. When, as the result of data reception, an error flag is set in asynchronous serial interface status register n (ASISn), the receive error interrupt request (INTSERn) is generated. -
Page 418: Standby Function
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.5.4 Standby function (1) Operation in HALT mode Serial transfer operations are performed normally. (2) Operation in STOP and IDLE modes (a) When internal clock is selected as serial clock The operations of asynchronous serial interface mode register n (ASIMn), transmit shift register n (TXSn), and receive buffer register n (RXBn) are stopped and their values immediately before the clock stopped are held. -
Page 419: 3-Wire Variable-Length Serial I/O (Csi4)
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.6 3-Wire Variable-Length Serial I/O (CSI4) CSI4 has the following two operation modes. (1) Operation stop mode This mode is used when serial transfers are not performed. (2) 3-wire variable-length serial I/O mode (MSB/LSB first switchable) This mode transfers variable data of 8 to 16 bits via three lines: serial clock (SCK4), serial output (SO4), and serial input (SI4). -
Page 420: Block Diagram Of Csi4
CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-55. Block Diagram of CSI4 Internal bus Direction controller Variable-length I/O shift register 4 (8-/16-bit) Serial clock counter Interrupt INTCSI4 (8-/16-bit switchable) generator Baud rate Serial clock controller Selector generator SCK4 (1) Variable-length serial I/O shift register 4 (SIO4) SIO4 is a 16-bit variable register that performs parallel-serial conversion and transmit/receive (shift operations) synchronized with the serial clock. -
Page 421: When Transfer Bit Length Other Than 16 Bits Is Set
CHAPTER 10 SERIAL INTERFACE FUNCTION When the transfer bit length is set to other than 16 bits and data is set to the shift register, data should be aligned from the lowest bit of the shift register, regardless of whether MSB or LSB is set for the first transfer bit. Any data can be set to the unused higher bits;... -
Page 422: Csi4 Control Registers
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.6.2 CSI4 control registers CSI4 uses the following registers for control functions. • Variable-length serial control register 4 (CSIM4) • Variable-length serial setting register 4 (CSIB4) • Baud rate generator source clock selection register 4 (BRGCN4) •... - Page 423 CHAPTER 10 SERIAL INTERFACE FUNCTION (2) Variable-length serial setting register 4 (CSIB4) CSIB4 is used to set the operation format of serial interface channel 4. The bit length of a variable register is set by setting bits 3 to 0 (BSEL3 to BSEL0) of variable-length serial setting register 4.
- Page 424 CHAPTER 10 SERIAL INTERFACE FUNCTION (3) Baud rate generator source clock selection register 4 (BRGCN4) BRGCN4 can be set by an 8-bit memory manipulation instruction. RESET input clears BRGCN4 to 00H. After reset: 00H Address: FFFFF2E6H BRGCN4 BRGN2 BRGN1 BRGN0 BRGN2 BRGN1 BRGN0...
- Page 425 CHAPTER 10 SERIAL INTERFACE FUNCTION (4) Baud rate generator output clock selection register 4 (BRGCK4) BRGCK4 is set by an 8-bit memory manipulation instruction. RESET input sets BRGCK4 to 7FH. After reset: 7FH Address: FFFFF2E8H BRGCK4 BRGK6 BRGK5 BRGK4 BRGK3 BRGK2 BRGK1 BRGK0...
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Page 426: Operations
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.6.3 Operations CSI4 has the following two operation modes. • Operation stop mode • 3-wire variable-length serial I/O mode (1) Operation stop mode In this mode serial transfers are not performed and therefore power consumption can be reduced. When in operation stop mode, SI4, SO4, and SCK4 can be used as normal I/O ports. -
Page 427: Csim4 Setting (3-Wire Variable-Length Serial I/O Mode)
CHAPTER 10 SERIAL INTERFACE FUNCTION (2) 3-wire variable-length serial I/O mode The 3-wire variable-length serial I/O mode is useful when connecting to a peripheral I/O device that includes a clocked serial interface, a display controller, etc. This mode executes data transfers via three lines: a serial clock line (SCK4), serial output line (SO4), and serial input line (SI4). -
Page 428: Csib4 Setting (3-Wire Variable-Length Serial I/O Mode)
CHAPTER 10 SERIAL INTERFACE FUNCTION The bit length of a variable-length register is set by setting bits 3 to 0 (BSEL3 to BSEL0) of CSIB4. Data is transferred MSB first while bit 4 (DIR) is 1, and is transferred LSB first while DIR is 0. Figure 10-59. -
Page 429: Timing Of 3-Wire Variable-Length Serial I/O Mode
CHAPTER 10 SERIAL INTERFACE FUNCTION (b) Communication Operations In the 3-wire variable-length serial I/O mode, data is transmitted and received in 8 to 16-bit units, and is specified by setting bits 3 to 0 (BSEL3 to BSEL0) of variable-length serial setting register 4 (CSIB4). Each bit of data is transmitted or received in synchronization with the serial clock. -
Page 430: Timing Of 3-Wire Variable-Length Serial I/O Mode (When Csib4 = 08H)
CHAPTER 10 SERIAL INTERFACE FUNCTION (c) Transfer start A serial transfer becomes possible when the following two conditions have been satisfied. • The SIO4 operation control bit (CSIE4) = 1 • After a serial transfer, the internal serial clock is stopped. Serial transfer starts when the following operation is performed after the above two conditions have been satisfied. -
Page 431: Chapter 11 A/D Converter
The A/D converter converts analog input signals into digital values with a resolution of 10 bits, and can handle 12 channels of analog input signals (ANI0 to ANI11). The V850/SB1 and V850/SB2 support the low power consumption mode by low-speed conversion. (1) Hardware start Conversion is started by trigger input (ADTRG) (rising edge, falling edge, or both rising and falling edges can be specified). -
Page 432: Block Diagram Of A/D Converter
CHAPTER 11 A/D CONVERTER The block diagram is shown below. Figure 11-1. Block Diagram of A/D Converter ANI0 ANI1 ANI2 Sample & hold circuit ANI3 ANI4 Voltage comparator ANI5 ANI6 ANI7 ANI8 ANI9 ANI10 Successive ANI11 approximation register (SAR) Edge ADTRG Controller INTAD... -
Page 433: Configuration
CHAPTER 11 A/D CONVERTER 11.2 Configuration The A/D converter includes the following hardware. Table 11-1. Configuration of A/D Converter Item Configuration Analog input 12 channels (ANI0 to ANI11) Registers Successive approximation register (SAR) A/D conversion result register (ADCR) A/D conversion result register H (ADCRH): Only higher 8 bits can be read Control registers A/D converter mode register 1 (ADM1) - Page 434 CHAPTER 11 A/D CONVERTER (6) ANI0 to ANI11 pins These are analog input pins for the 12 channels of the A/D converter, and are used to input the analog signals to be converted into digital signals. Pins other than ones selected as the analog input by the analog input channel specification register (ADS) can be used as input ports.
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Page 435: Control Registers
CHAPTER 11 A/D CONVERTER 11.3 Control Registers The A/D converter is controlled by the following registers. • A/D converter mode register 1 (ADM1) • Analog input channel specification register (ADS) • A/D converter mode register 2 (ADM2) (1) A/D converter mode register 1 (ADM1) This register specifies the conversion time of the input analog signal to be converted into a digital signal, starting or stopping the conversion, and an external trigger. - Page 436 Each A/D conversion requires “conversion time + stabilization time”. There is no stabilization time when ADPS = 0. 3. Only in the V850/SB1. Cautions 1. The A/D converter cannot be used when the operation frequency is 2.4 to 3.6 MHz.
- Page 437 CHAPTER 11 A/D CONVERTER (2) Analog input channel specification register (ADS) ADS specifies the port for inputting the analog voltage to be converted into a digital signal. ADS is set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears ADS to 00H. After reset: Address: FFFFF3C2H ADS3...
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Page 438: Operation
CHAPTER 11 A/D CONVERTER 11.4 Operation 11.4.1 Basic operation <1> Select one channel whose analog signal is to be converted into a digital signal by using the analog input channel specification register (ADS). <2> The sample & hold circuit samples the voltage input to the selected analog input channel. <3>... -
Page 439: Basic Operation Of A/D Converter
CHAPTER 11 A/D CONVERTER Figure 11-2. Basic Operation of A/D Converter Conversion time Sampling time Operation of Sampling A/D conversion A/D converter Conversion Undefined result Conversion ADCR result INTAD A/D conversion is successively executed until bit 7 (ADCS) of A/D converter mode register 1 (ADM1) is reset to 0 by software. -
Page 440: Input Voltage And Conversion Result
CHAPTER 11 A/D CONVERTER 11.4.2 Input voltage and conversion result The analog voltages input to the analog input pins (ANI0 to ANI11) and the result of the A/D conversion (contents of the A/D conversion result register (ADCR)) are related as follows. ×... -
Page 441: A/D Converter Operation Mode
CHAPTER 11 A/D CONVERTER 11.4.3 A/D converter operation mode In this mode one of the analog input channels ANI0 to ANI11 is selected by the analog input channel specification register (ADS) and A/D conversion is executed. The A/D conversion can be started in the following two ways. •... -
Page 442: A/D Conversion By Software Start
CHAPTER 11 A/D CONVERTER (2) A/D conversion by software start If bit 6 (TRG) of A/D converter mode register 1 (ADM1) is set to 0 and bit 7 (ADCS) is set to 1, the A/D converter starts converting the voltage applied to the analog input pin specified by the analog input channel specification register (ADS) into a digital signal. -
Page 443: Low Power Consumption Mode
CHAPTER 11 A/D CONVERTER 11.5 Low Power Consumption Mode The V850/SB1 and V850/SB2 feature a function that can cut or connect the current between AV and AV Switching can be performed by setting A/D converter mode register 2 (ADM2). = AV... -
Page 444: Handling Of Analog Input Pin
CHAPTER 11 A/D CONVERTER (4) Countermeasures against noise To keep the resolution of 10 bits, prevent noise from being superimposed on the AV and ANI0 to ANI11 pins. The higher the output impedance of the analog input source, the heavier the influence of noise. To lower noise, connecting an external capacitor as shown in Figure 11-6 is recommended. -
Page 445: A/D Conversion End Interrupt Generation Timing
CHAPTER 11 A/D CONVERTER (7) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the contents of the analog input channel specification register (ADS) are changed. If the analog input pin is changed during conversion, therefore, the result of the A/D conversion of the preceding analog input signal and the conversion end interrupt request flag may be set immediately before ADS is rewritten. -
Page 446: Dd Pin
CHAPTER 11 A/D CONVERTER (8) AV The AV pin is the power supply pin of the analog circuit, and also supplies power to the input circuit of ANI0 to ANI11. Even in an application where a backup power supply is used, therefore, be sure to apply the same voltage as the V pin to the AV pin as shown in Figure 11-8. -
Page 447: How To Read A/D Converter Characteristics Table
CHAPTER 11 A/D CONVERTER 11.7 How to Read A/D Converter Characteristics Table Here, special terms unique to the A/D converter are explained. (1) Resolution This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage per bit of digital output is called 1LSB (Least Significant Bit). -
Page 448: Quantization Error
CHAPTER 11 A/D CONVERTER (3) Quantization error When analog values are converted to digital values, a ±1/2LSB error naturally occurs. In an A/D converter, an analog input voltage in a range of ±1/2LSB is converted to the same digital code, so a quantization error cannot be avoided. -
Page 449: Full-Scale Error
CHAPTER 11 A/D CONVERTER (5) Full-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (3/2LSB) when the digital output changes from 1……110 to 1……111. Figure 11-12. Full-Scale Error Full-scale error –3 –2 –1... -
Page 450: Integral Linearity Error
CHAPTER 11 A/D CONVERTER (7) Integral linearity error This shows the degree to which the conversion characteristics deviate from the ideal linear relationship. It expresses the maximum value of the difference between the actual measurement value and the ideal straight line when the zero-scale error and full-scale error are 0. Figure 11-14. -
Page 451: Chapter 12 Dma Functions
CHAPTER 12 DMA FUNCTIONS 12.1 Functions The DMA (Direct Memory Access) controller transfers data between memory and peripheral I/Os based on DMA requests sent from on-chip peripheral hardware (such as the serial interface, timer, or A/D converter). This product includes six independent DMA channels that can transfer data in 8-bit and 16-bit units. maximum number of transfers is 256 (when transferring data in 8-bit units). -
Page 452: Configuration
CHAPTER 12 DMA FUNCTIONS 12.3 Configuration Figure 12-1. Block Diagram of DMA DMA transfer trigger DMA transfer (INT signal) request control DMA peripheral I/O address DMA channel control register n (DIOAn) register n (DCHCn) DMA byte count DMA transfer acknowledge signal register n (DBCn) Channel controller DMA internal RAM address... -
Page 453: Control Registers
CHAPTER 12 DMA FUNCTIONS 12.4 Control Registers (1) DMA peripheral I/O address registers 0 to 5 (DIOA0 to DIOA5) These registers are used to set the peripheral I/O register address for DMA channel n. These registers are can be read/written in 16-bit units. After reset: Undefined Address:... - Page 454 Table 12-1. Internal RAM Area Usable in DMA Product Internal RAM RAM Size RAM Area Usable in DMA Capacity Usable in DMA µ PD703031B, 703031BY V850/SB1 8 KB 8 KB xxFFD000H to xxFFEFFFH µ PD703034B, 703034BY V850/SB2 µ PD703031A, 703031AY, V850/SB1...
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Page 455: Correspondence Between Dran Setting Value And Internal Ram (8 Kb)
The correspondence between DRAn setting value and internal RAM area is shown below. (a) V850/SB1 ( µ µ µ µ PD703031B, 703031BY), V850/SB2 ( µ µ µ µ PD703034B, 703034BY) Set the DRAn register to a value in the range of 0000H to 1FFFH (n = 0 to 5). -
Page 456: Correspondence Between Dran Setting Value And Internal Ram (12 Kb)
CHAPTER 12 DMA FUNCTIONS (b) V850/SB1 ( µ µ µ µ PD703031A, 703031AY), V850/SB2 ( µ µ µ µ PD703034A, 703034AY) Set the DRAn register to a value in the range of 0000H to 2FFFH (n = 0 to 5). -
Page 457: Correspondence Between Dran Setting Value And Internal Ram (16 Kb)
CHAPTER 12 DMA FUNCTIONS (c) V850/SB1 ( µ µ µ µ PD703033A, 703033AY, 703033B, 703033BY, 70F3033A, 70F3033AY, 70F3033B, 70F3033BY) V850/SB2 ( µ µ µ µ PD703035A, 703035AY, 703035B, 703035BY, 70F3035A, 70F3035AY, 70F3035B, 70F3035BY) Set the DRAn register to a value in the range of 000H to 2FFFH or 3000H to 3FFFH (n = 0 to 5). -
Page 458: Correspondence Between Dran Setting Value And Internal Ram (24 Kb)
CHAPTER 12 DMA FUNCTIONS (d) V850/SB1 ( µ µ µ µ PD703030B, 703030BY, 703032A, 703032AY, 703032B, 703032BY, 70F3030B, 70F3030BY, 70F3032A, 70F3032AY, 70F3032B, 70F3032BY) V850/SB2 ( µ µ µ µ PD703036H, 703036HY, 703037A, 703037AY, 703037H, 703037HY, 70F3036H, 70F3036HY, 70F3037A, 70F3037AY, 70F3037H, 70F3037HY) Set the DRAn register to a value in the range of 0000H to 0FFFH or 1000H to 3FFFH (n = 0 to 5). - Page 459 CHAPTER 12 DMA FUNCTIONS (3) DMA byte count registers 0 to 5 (DBC0 to DBC5) These are 8-bit registers that are used to set the number of transfers for DMA channel n. The remaining number of transfers is retained during the DMA transfers. A value of 1 is decremented once per transfer if the transfer is a byte (8-bit) transfer, and a value of 2 is decremented once per transfer if the transfer is a 16-bit transfer.
- Page 460 CHAPTER 12 DMA FUNCTIONS (5) DMA channel control registers 0 to 5 (DCHC0 to DCHC5) These registers are used to control the DMA transfer operation mode for DMA channel n. These registers are can be read/written in 1-bit or 8-bit units. (1/2) After reset: Address:...
- Page 461 CHAPTER 12 DMA FUNCTIONS (2/2) Channel n DMAS2 DMAS1 DMAS0 TTYPn1 TTYPn0 DMA transfer start factor setting INTST1 INTCSI4 INTAD INTTM2 INTCSI3/INTSR1 INTCSI4 INTCSI2 INTTM6 Note 3 TDIRn Transfer direction control between peripheral I/Os and internal RAM From internal RAM to peripheral I/Os From peripheral I/Os to internal RAM Note 3 Control of transfer data size for DMA transfer...
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Page 462: Operation
CHAPTER 12 DMA FUNCTIONS 12.5 Operation When a DMA transfer request is generated during CPU processing, DMA transfer is started after the current CPU processing has finished. Regardless of the transfer direction, 4 CPU clocks (f ) are required for one DMA transfer. The 4 CPU clocks are divided as follows. -
Page 463: Cautions
CHAPTER 12 DMA FUNCTIONS Figure 12-7. Processing When Transfer Requests DMA0 to DMA5 Are Generated Simultaneously DAM0 DAM1 DAM2 DAM3 DAM4 DAM5 processing processing processing processing processing processing processing processing processing processing processing processing processing Transfer requests DMA0 to DMA5 are generated simultaneously DMA operation stops only in the IDLE/STOP mode. -
Page 464: When Interrupt Servicing Occurs Twice During Dma Operation
CHAPTER 12 DMA FUNCTIONS Figure 12-8. When Interrupt Servicing Occurs Twice During DMA Operation (1/2) (a) Normal interrupt servicing Interrupt servicing routine Main routine Interrupt request flag (xxIFn) is cleared (0). Interrupt request RETI (b) Interrupt servicing when interrupt servicing occurs twice Interrupt servicing routine Main routine Interrupt request flag (xxIFn) is... - Page 465 CHAPTER 12 DMA FUNCTIONS Figure 12-8. When Interrupt Servicing Occurs Twice During DMA Operation (2/2) (c) Countermeasure (use condition (i)) Main routine Interrupt servicing routine Interrupt request flag (xxIFn) is cleared (0). Bit manipulation instruction to xxIFn Interrupt request The interrupt is serviced in the EI state (interrupt enable state) (the interrupt is not serviced immediately after bit manipulation instruction execution).
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Page 466: Chapter 13 Real-Time Output Function (Rto)
REAL-TIME OUTPUT FUNCTION (RTO) 13.1 Function The V850/SB1 and V850/SB2 incorporate a real-time output function (RTO) that transfers preset data to real-time output buffer registers (RTBL, RTBH) and then transfers this data with hardware to an external device via the output latches, upon the occurrence of an external interrupt or external trigger. -
Page 467: Configuration
CHAPTER 13 REAL-TIME OUTPUT FUNCTION (RTO) 13.3 Configuration A block diagram of RTO is shown below. Figure 13-1. Block Diagram of RTO Internal bus Real-time output port control register (RTPC) RTPOE RTPEG BYTE EXTR RTPTRG Real-time output Real-time output Output trigger INTTM4 buffer register, higher buffer register, lower... -
Page 468: Configuration Of Real-Time Output Buffer Registers
CHAPTER 13 REAL-TIME OUTPUT FUNCTION (RTO) (1) Real-time output buffer registers (RTBL, RTBH) RTBL and RTBH are 4-bit registers that hold output data in advance. These registers are mapped to independent addresses in the peripheral I/O register area as shown in Figure 13- If an operation mode of 4 bits ×... -
Page 469: Rto Control Registers
CHAPTER 13 REAL-TIME OUTPUT FUNCTION (RTO) 13.4 RTO Control Registers RTO is controlled by using the following two types of registers. • Real-time output port mode register (RTPM) • Real-time output port control register (RTPC) (1) Real-time output port mode register (RTPM) This register selects real-time output port mode or port mode in 1-bit units. - Page 470 CHAPTER 13 REAL-TIME OUTPUT FUNCTION (RTO) (2) Real-time output port control register (RTPC) This register sets the operation mode and output trigger of the real-time output port. The relationship between the operation mode and output trigger of the real-time output port is as shown in Table 13- RTPC is set by an 8-bit or 1-bit memory manipulation instruction.
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Page 471: Usage
CHAPTER 13 REAL-TIME OUTPUT FUNCTION (RTO) 13.5 Usage (1) Disable the real-time output operation. Clear bit 7 (RTPOE) of the real-time output port control register (RTPC) to 0. (2) Initial setting Set the value to be output first to the real-time output port to the output latch of port 10. (ii) Set the PM10 register to output mode. -
Page 472: Operation
CHAPTER 13 REAL-TIME OUTPUT FUNCTION (RTO) 13.6 Operation If the real-time output operation is enabled by setting bit 7 (RTPOE) of the real-time output port control register (RTPC) to 1, the data of the real-time output buffer registers (RTBH and RTBL) is transferred to the output latch in Note synchronization with the generation of the selected transmit trigger (set by EXTR and BYTE ). -
Page 473: Cautions
CHAPTER 13 REAL-TIME OUTPUT FUNCTION (RTO) 13.7 Cautions (1) Before performing initialization, disable the real-time output operation by clearing bit 7 (RTPOE) of the real-time output port control register (RTPC) to 0. (2) Once the real-time output operation is disabled (RTPOE = 0), be sure to set the same initial value as the output latch to the real-time output buffer registers (RTBH and RTBL) before enabling the real-time output operation (RTPOE = 0 →... -
Page 474: Chapter 14 Port Function
CHAPTER 14 PORT FUNCTION 14.1 Port Configuration The V850/SB1 and V850/SB2 include 83 I/O port pins from ports 0 to 11 (12 port pins are input only). There are three power supplies for the I/O buffers: AV , BV , and EV , which are described below. - Page 475 CHAPTER 14 PORT FUNCTION Port 0 includes the following alternate functions. Table 14-2. Port 0 Alternate Function Pins Note Pin Name Alternate Function PULL Remark Port 0 Analog noise elimination INTP0 INTP1 INTP2 INTP3 INTP4/ADTRG Digital noise elimination INTP5/RTPTRG INTP6 Note Software pull-up function (1) Function of P0 pins Port 0 is an 8-bit I/O port for which I/O settings can be controlled in 1-bit units.
- Page 476 CHAPTER 14 PORT FUNCTION Cautions 1. If the input pulse width is 2 to 3 clocks, whether it will be detected as a valid edge or eliminated as noise is undefined. 2. To ensure correct detection of pulses as pulses, constant-level input is required for 3 clocks or more.
- Page 477 CHAPTER 14 PORT FUNCTION (c) Rising edge specification register 0 (EGP0) EGP0 can be read/written in 8-bit or 1-bit units. After reset: Address: FFFFF0C0H <7> <6> <5> <4> <3> <2> <1> <0> EGP0 EGP07 EGP06 EGP05 EGP04 EGP03 EGP02 EGP01 EGP00 EGP0n Control of rising edge detection (n = 0 to 7)
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Page 478: Block Diagram Of P00 To P07
CHAPTER 14 PORT FUNCTION (4) Block diagram (Port 0) Figure 14-1. Block Diagram of P00 to P07 P-ch PU0n Selector P00/NMI P01/INTP0 PORT P02/INTP1 Output latch P03/INTP2 (P0n) P04/INTP3 P05/INTP4/ADTRG P06/INTP5/RTPTRG P07/INTP6 PM0n Remarks 1. PU0: Pull-up resistor option register 0 PM0: Port 0 mode register Port 0 read signal Port 0 write signal... -
Page 479: Port 1
CHAPTER 14 PORT FUNCTION 14.2.2 Port 1 Port 1 is a 6-bit I/O port for which I/O settings can be controlled in 1-bit units. A pull-up resistor can be connected in 1-bit units (software pull-up function). Bits 0, 1, 2, 4, and 5 are selectable as normal outputs or N-ch open-drain outputs. After reset: Address: FFFFF002H Control of output data (in output mode) (n = 0 to 5) - Page 480 CHAPTER 14 PORT FUNCTION (1) Function of P1 pins Port 1 is a 6-bit I/O port for which I/O settings can be controlled in 1-bit units. I/O settings are controlled via the port 1 mode register (PM1). In output mode, the values set to each bit are output to the port 1 register (P1). The port 1 function register (PF1) can be used to specify whether P10 to P12, P14, and P15 are normal outputs or N-ch open-drain outputs.
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Page 481: Block Diagram Of P10 To P12, P14, And P15
CHAPTER 14 PORT FUNCTION (c) Port 1 function register (PF1) PF1 can be read/written in 8-bit or 1-bit units. After reset: Address: FFFFF0A2H Note PF15 PF14 PF12 PF11 PF10 PF1n Control of normal output/N-ch open-drain output (n = 0 to 2, 4, 5) Normal output N-ch open-drain output Note Bit 3 is fixed as a normal output. -
Page 482: Block Diagram Of P13
CHAPTER 14 PORT FUNCTION Figure 14-3. Block Diagram of P13 PU13 P-ch Selector PORT Output latch (P13) P13/SI1/RxD0 PM13 Alternate function Remark PU1: Pull-up resistor option register 1 PM1: Port 1 mode register Port 1 read signal Port 1 write signal User’s Manual U13850EJ6V0UD... -
Page 483: Port 2
CHAPTER 14 PORT FUNCTION 14.2.3 Port 2 Port 2 is an 8-bit I/O port for which I/O settings can be controlled in 1-bit units. A pull-up resistor can be connected in 1-bit units (software pull-up function). P20, P21, P22, P24 and P25 are selectable as normal outputs or N-ch open-drain outputs. When P26 and P27 are used as the TI2 and TI3 pins, noise is eliminated from these pins by a digital noise eliminator. - Page 484 CHAPTER 14 PORT FUNCTION (1) Function of P2 pins Port 2 is an 8-bit I/O port for which I/O settings can be controlled in 1-bit units. I/O settings are controlled via the port 2 mode register (PM2). In output mode, the values set to each bit are output to the port 2 register (P2). The port 2 function register (PF2) can be used to specify whether P20, P21, P22, P24 and P25 are normal outputs or N-ch open-drain outputs.
- Page 485 CHAPTER 14 PORT FUNCTION (b) Pull-up resistor option register 2 (PU2) PU2 can be read/written in 8-bit or 1-bit units. After reset: Address: FFFFF084H PU27 PU26 PU25 PU24 PU23 PU22 PU21 PU20 PU2n Control of on-chip pull-up resistor connection (n = 0 to 7) Do not connect Connect (c) Port 2 function register (PF2)
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Page 486: Block Diagram Of P20 To P22, P24, And P25
CHAPTER 14 PORT FUNCTION (3) Block diagram (Port 2) Figure 14-4. Block Diagram of P20 to P22, P24, and P25 P-ch PU2n Selector PF2n PORT Note P20/SI2/SDA1 Output latch P-ch P21/SO2 (P2n) P22/SCK2/SCL1 Note P24/SO3/TxD1 N-ch P25/SCK3/ASCK1 PM2n Alternate function Note The SDA1 and SCL1 pins are available only in the Y versions (products with on-chip I Remarks 1. -
Page 487: Block Diagram Of P23, P26, And P27
CHAPTER 14 PORT FUNCTION Figure 14-5. Block Diagram of P23, P26, and P27 PU13 P-ch Selector PORT Output latch (P13) P13/SI1/RxD0 PM13 Alternate function Remarks 1. PU2: Pull-up resistor option register 2 PM2: Port 2 mode register Port 2 read signal Port 2 write signal 2. -
Page 488: Port 3
CHAPTER 14 PORT FUNCTION 14.2.4 Port 3 Port 3 is an 8-bit I/O port for which I/O settings can be controlled in 1-bit units. A pull-up resistor can be connected in 1-bit units (software pull-up function). Either a normal output or N-ch open-drain out can be selected for P33 and P34. When using P36 and P37 as the TI4 and TI5 pins, noise is eliminated by the digital noise eliminator. - Page 489 CHAPTER 14 PORT FUNCTION (1) Function of P3 pins Port 3 is an 8-bit I/O port for which I/O settings can be controlled in 1-bit units. I/O settings are controlled via the port 3 mode register (PM3). In output mode, the values set to each bit are output to the port 3 register (P3). The port 3 function register (PF3) can be used to specify whether P33 and P34 are normal outputs or N-ch open-drain outputs.
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Page 490: Block Diagram Of P30 To P32 And P35 To P37
CHAPTER 14 PORT FUNCTION (c) Port 3 function register (PF3) PF3 can be read/written in 8-bit or 1-bit units. After reset: Address: FFFFF0A6H PF34 PF33 PF3n Control of normal output/N-ch open-drain output (n = 3, 4) Normal output N-ch open-drain output (3) Block diagram (Port 3) Figure 14-6. -
Page 491: Block Diagram Of P33 And P34
CHAPTER 14 PORT FUNCTION Figure 14-7. Block Diagram of P33 and P34 PU3n P-ch Selector PF3n PORT Output latch P-ch (P3n) P33/TI11/SO4 P34/TO0/A13/SCK4 N-ch PM3n Alternate function Remarks 1. PU3: Pull-up resistor option register 3 RF3: Port 3 function register PM3: Port 3 mode register Port 3 read signal Port 3 write signal... -
Page 492: Ports 4 And 5
CHAPTER 14 PORT FUNCTION 14.2.5 Ports 4 and 5 Ports 4 and 5 are 8-bit I/O ports for which I/O settings can be controlled in 1-bit units. After reset: Address: FFFFF008H, FFFFF00AH Control of output data (in output mode) (n = 4, 5, x = 0 to 7) Output 0 Output 1 Remark... - Page 493 CHAPTER 14 PORT FUNCTION (1) Functions of P4 and P5 pins Ports 4 and 5 are 8-bit I/O ports for which I/O settings can be controlled in 1-bit units. I/O settings are controlled via the port 4 mode register (PM4) the and port 5 mode register (PM5). In output mode, the values set to each bit are output to the port 4 and 5 registers (P4 and P5).
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Page 494: Block Diagram Of P40 To P47 And P50 To P57
CHAPTER 14 PORT FUNCTION (3) Block diagram (Ports 4 and 5) Figure 14-8. Block Diagram of P40 to P47 and P50 to P57 Selector PORT Output latch Pmn/ADx (mn) PMmn Remarks 1. PMm: Port m mode register Port m read signal Port m write signal 2. -
Page 495: Port 6
CHAPTER 14 PORT FUNCTION 14.2.6 Port 6 Port 6 is a 6-bit I/O port for which I/O settings can be controlled in 1-bit units. After reset: Address: FFFFF00CH Control of output data (in output mode) (n = 0 to 5) Outputs 0 Outputs 1 Remark... - Page 496 CHAPTER 14 PORT FUNCTION (1) Function of P6 pins Port 6 is a 6-bit I/O port for which I/O settings can be controlled in 1-bit units. I/O settings are controlled via the port 6 mode register (PM6). In output mode, the values set to each bit are output to the port 6 register (P6). When using this port in input mode, the pin statuses can be read by reading the P6 register.
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Page 497: Block Diagram P60 To P65
CHAPTER 14 PORT FUNCTION (3) Block diagram (Port 6) Figure 14-9. Block Diagram P60 to P65 Selector PORT Output latch P6n/Ax (P6n) PM6n Remarks 1. PM6: Port 6 mode register Port 6 read signal Port 6 write signal 2. n = 0 to 5 x = 16 to 21 User’s Manual U13850EJ6V0UD... -
Page 498: Ports 7 And 8
CHAPTER 14 PORT FUNCTION 14.2.7 Ports 7 and 8 Port 7 is an 8-bit input port and port 8 is a 4-bit input port. Both ports are read-only and are accessible in 8-bit or 1-bit units. After reset: Undefined Address: FFFFF00EH Pin level (n = 0 to 7) Read pin level of bit n After reset:... -
Page 499: Block Diagram Of P70 To P77 And P80 To P83
CHAPTER 14 PORT FUNCTION (1) Functions of P7 and P8 pins Port 7 is an 8-bit input-only port and port 8 is a 4-bit input-only port. The pin statuses can be read by reading the port 7 and 8 registers (P7 and P8). Data cannot be written to P7 or A software pull-up function is not implemented. -
Page 500: Port 9
CHAPTER 14 PORT FUNCTION 14.2.8 Port 9 Port 9 is a 7-bit I/O port for which I/O settings can be controlled in 1-bit units. After reset: Address: FFFFF012H Control of output data (in output mode) (n = 0 to 6) Output 0 Output 1 Remark... - Page 501 CHAPTER 14 PORT FUNCTION (1) Function of P9 pins Port 9 is a 7-bit I/O port for which I/O settings can be controlled in 1-bit units. I/O settings are controlled via the port 9 mode register (PM9). In output mode, the values set to each bit are output to the port 9 register (P9). When using this port in input mode, the pin statuses can be read by reading the P9 register.
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Page 502: Block Diagram Of P90 To P96
CHAPTER 14 PORT FUNCTION (3) Block diagram (Port 9) Figure 14-11. Block Diagram of P90 to P96 Selector P90/LBEN/WRL PORT P91/UBEN P92/R/W/WRH Output latch P93/DSTB/RD (P9n) P94/ASTB P95/HLDAK P96/HLDRQ PM9n Remarks 1. PM9: Port 9 mode register Port 9 read signal Port 9 write signal 2. -
Page 503: Port 10
CHAPTER 14 PORT FUNCTION 14.2.9 Port 10 Port 10 is an 8-bit I/O port for which I/O settings can be controlled in 1-bit units. A pull-up resistor can be connected in 1-bit units (software pull-up function). The pins in this port are selectable as normal outputs or N-ch open-drain outputs. When using P100 to P107 as KR0 to KR7 pins, noise is eliminated by the analog noise eliminator. - Page 504 CHAPTER 14 PORT FUNCTION (1) Function of P10 pins Port 10 is an 8-bit I/O port for which I/O settings can be controlled in 1-bit units. I/O settings are controlled via the port 10 mode register (PM10). In output mode, the values set to each bit are output to the port 10 register (P10). The port 10 function register (PF10) can be used to specify whether outputs are normal outputs or N-ch open-drain outputs.
- Page 505 CHAPTER 14 PORT FUNCTION (c) Port 10 function register (PF10) PF10 can be read/written in 8-bit or 1-bit units. After reset: Address: FFFFF0B4H PF10 PF107 PF106 PF105 PF104 PF103 PF102 PF101 PF100 PF10n Control of normal output/N-ch open-drain output (n = 0 to 7) Normal output N-ch open-drain output User’s Manual U13850EJ6V0UD...
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Page 506: Block Diagram Of P100 To P107
CHAPTER 14 PORT FUNCTION (3) Block diagram (Port 10) Figure 14-12. Block Diagram of P100 to P107 PU10 P-ch PU10n Selector PF10 PF10n P100/RTP0/A5/KR0 PORT P101/RTP1/A6/KR1 Output latch P102/RTP2/A7/KR2 P-ch (P10n) P103/RTP3/A8/KR3 Note P104/RTP4/A9/KR4/IERX PM10 N-ch Note P105/RTP5/A10/KR5/IETX P106/RTP6/A11/KR6 PM10n P107/RTP7/A12/KR7 Alternate function Note... -
Page 507: Port 11
CHAPTER 14 PORT FUNCTION 14.2.10 Port 11 Port 11 is a 4-bit port. A pull-up resistor can be connected to bits 0 to 3 in 1-bit units (software pull-up function). P11 can be read/written in 8-bit or 1-bit units. The on/off of wait function can be switched with a port alternate-function control register (PAC). Caution When using the wait function, set BC to the same potential as EV... - Page 508 CHAPTER 14 PORT FUNCTION (1) Function of P11 pins Port 11 is a 4-bit (total) port for which I/O settings can be controlled in 1-bit units. In output mode, the values set to each bit (bit 0 to bit 3) are output to the port register (P11). When using this port in input mode, the pin statuses can be read by reading the P11 register.
- Page 509 CHAPTER 14 PORT FUNCTION (b) Pull-up resistor option register 11 (PU11) PU11 can be read/written in 8-bit or 1-bit units. After reset: Address: FFFFF096H PU11 PU113 PU112 PU111 PU110 PU11n Control of on-chip pull-up resistor connection (n = 0 to 3) Do not connect Connect (c) Port alternate-function control register (PAC)
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Page 510: Block Diagram Of P110 To P113
CHAPTER 14 PORT FUNCTION (3) Block diagram (Port 11) Figure 14-13. Block Diagram of P110 to P113 PU11 PU11n P-ch Selector PORT P110/A1/WAIT P111/A2 Output latch P112/A3 (P11n) P113/A4 PM11 PM11n Remarks 1. PU11: Pull-up resistor option register 11 PM11: Port 11 mode register Port 11 read signal Port 11 write signal 2. -
Page 511: Setting When Port Pin Is Used As Alternate Function
CHAPTER 14 PORT FUNCTION 14.3 Setting When Port Pin Is Used as Alternate Function When a port pin is used as an alternate function, set the port n mode register (PM0 to PM6 and PM9 to PM11) and output latch as shown in Table 14-12 below. Table 14-12. - Page 512 CHAPTER 14 PORT FUNCTION Table 14-12. Setting When Port Pin Is Used as Alternate Function (2/4) PMnx Bit of Pnx Bit of Other Bits Pin Name Alternate Function PMn Register Pn Register (Register) Function Name Input PM20 = 1 Setting not needed for P20 Note...
- Page 513 CHAPTER 14 PORT FUNCTION Table 14-12. Setting When Port Pin Is Used as Alternate Function (3/4) PMnx Bit of Pnx Bit of Other Bits Pin Name Alternate Function PMn Register Pn Register (Register) Function Name Output PM35 = 0 P35 = 0 Refer to 3.4.6 (2) (MAM) Output...
- Page 514 CHAPTER 14 PORT FUNCTION Table 14-12. Setting When Port Pin Is Used as Alternate Function (4/4) PMnx Bit of Pnx Bit of Other Bits Pin Name Alternate Function PMn Register Pn Register (Register) Function Name P100 to P103 RTP0 to RTP3 Output PM100 to PM103 = 0 P100 to P103 = 0...
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Page 515: Port Function Operation
CHAPTER 14 PORT FUNCTION 14.4 Port Function Operation Port operation differs according to the input/output mode setting, as follows. 14.4.1 Write operation to I/O port (1) In output mode A value is written to the output latch using a transfer instruction, and the contents of the output latch are output from the pin. -
Page 516: Chapter 15 Reset Function
CHAPTER 15 RESET FUNCTION 15.1 General When a low level is input to the RESET pin, a system reset is performed and the various on-chip hardware devices are reset to their initial settings. In addition, oscillation of the main clock is stopped during the reset period, although oscillation of the subclock continues. -
Page 517: Chapter 16 Regulator
CHAPTER 16 REGULATOR 16.1 Outline The V850/SB1 and V850/SB2 incorporate a regulator to realize a 5 V single power supply, low power consumption, and to reduce noise. This regulator supplies a voltage obtained by stepping down the V power supply voltage to the oscillation blocks and on-chip logic circuits (excluding the A/D converter and output buffers). -
Page 518: Chapter 17 Rom Correction Function
ROM CORRECTION FUNCTION 17.1 General The ROM correction function provided in the V850/SB1 and V850/SB2 is a function that replaces part of a program in the mask ROM with a program in the internal RAM. First, the instruction of the address where the program replacement should start is replaced with the JMP r0 instruction and the program is instructed to jump to 00000000H. -
Page 519: Rom Correction Peripheral I/O Registers
CHAPTER 17 ROM CORRECTION FUNCTION 17.2 ROM Correction Peripheral I/O Registers (1) Correction control register (CORCN) CORCN controls whether or not the instruction of the correction address is replaced with the JMP r0 instruction when the correction address matches the fetch address (n = 0 to 3). Whether match detection by a comparator is enabled or disabled can be set for each channel. - Page 520 CHAPTER 17 ROM CORRECTION FUNCTION (2) Correction request register (CORRQ) CORRQ saves the channel in which ROM correction occurred. The JMP r0 instruction makes the program jump to 00000000H after the correction address matches the fetch address. At this time, the program can judge the following cases by reading CORRQ.
- Page 521 CORADn sets the start address of an instruction to be corrected (correction address) in the ROM. Up to four points of the program can be corrected at once since the V850/SB1 and V850/SB2 have four correction address registers (CORADn) (n = 0 to 3).
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Page 522: Rom Correction Operation And Program Flow
CHAPTER 17 ROM CORRECTION FUNCTION Figure 17-2. ROM Correction Operation and Program Flow START (reset vector) CORRQn = 0? Microcontroller initialization Clears CORRQn flag. JMP channel n correct code address The address of the internal RAM that Data for ROM correction setting is loaded stores the correction code of channel n from an external memory into the internal should be preset before the instruction... -
Page 523: Chapter 18 Flash Memory
The following can be considered as the development environment and applications using flash memory. • Software can be altered after the V850/SB1 or V850/SB2 is solder-mounted on the target system. • Small scale production of various models is made easier by differentiating software. -
Page 524: Erase Unit
18.1.1 Erase unit The erase unit differs depending on the product. (1) V850/SB1 ( µ µ µ µ PD70F3033A, 70F3033AY, 70F3033B, 70F3033BY), V850/SB2 ( µ µ µ µ PD70F3035A, 70F3035AY, 70F3035B, 70F3035BY) The erase units for 256 KB flash memory versions are shown below. -
Page 525: Writing With Flash Programmer
Writing can be performed either on-board or off-board with the dedicated flash programmer. (1) On-board programming The contents of the flash memory are rewritten after the V850/SB1 or V850/SB2 is mounted on the target system. Mount connectors, etc., on the target system to connect the dedicated flash programmer. - Page 526 Connect to VDD. /RESET VPP RESERVE/HS Note The V850/SB1 and V850/SB2 cannot be supplied with the clock from the CLK pin of the flash programmer (PG-FP3). Supply the clock by creating an oscillator on the flash writing adapter (broken-line portion).
- Page 527 P00/NMI P00/NMI P00/NMI Note The V850/SB1 and V850/SB2 cannot be supplied with the clock from the CLK pin of the flash programmer (PG-FP3). Supply the clock by creating an oscillator on the flash writing adapter (broken-line portion). User’s Manual U13850EJ6V0UD...
- Page 528 Connect to VDD. 9 10 /RESET VPP RESERVE/HS Note The V850/SB1 and V850/SB2 cannot be supplied with the clock from the CLK pin of the flash programmer (PG-FP3). Supply a clock by creating an oscillator on the flash writing adapter (broken-line portion).
- Page 529 P00/NMI P00/NMI P00/NMI Note The V850/SB1 and V850/SB2 cannot be supplied with the clock from the CLK pin of the flash programmer (PG-FP3). Supply the clock by creating an oscillator on the flash writing adapter (broken-line portion). User’s Manual U13850EJ6V0UD...
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Page 530: Programming Environment
A host machine is required for controlling the dedicated flash programmer. UART0 or CSI0 is used for the interface between the dedicated flash programmer and the V850/SB1 or V850/SB2 to perform writing, erasing, etc. A dedicated program adapter (FA Series) required for off-board writing. - Page 531 The dedicated flash programmer outputs the transfer clock, and the V850/SB1 and V850/SB2 operate as slaves. When the PG-FP3 is used as the dedicated flash programmer, it generates the following signals to the V850/SB1 or V850/SB2 . For details, refer to the PG-FP3 User’s Manual.
- Page 532 Pin Function Pin Name CSI0 UART0 Output Writing voltage voltage generation/ voltage monitoring − Ground × × × Note Output Clock output to V850/SB1, V850/SB2 RESET Output Reset signal RESET SI/RxD Input Receive signal SO0/TxD0 SO/TxD Output Transmit signal SI0/RxD0 ×...
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Page 533: Pin Connection
The following shows an example of the connection of the V pin. Figure 18-7. V Pin Connection Example V850/SB1, V850/SB2 Dedicated flash programmer connection pin Pull-down resistor (R 18.5.2 Serial interface pin The following shows the pins used by each serial interface. - Page 534 (output), conflict of signals occurs. To avoid the conflict of signals, isolate the connection to the other device or set the other device to the output high-impedance status. Figure 18-8. Conflict of Signals (Serial Interface Input Pin) V850/SB1, V850/SB2 Conflict of signals Dedicated flash programmer connection pins...
- Page 535 Dedicated flash programmer connection pin Other device Input pin In the flash memory programming mode, if the signal the V850/SB1 or V850/SB2 outputs affects the other device, isolate the signal on the other device side. V850/SB1, V850/SB2 Dedicated flash programmer connection pin...
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Page 536: Reset Pin
When a reset signal is input from the user system in the flash memory programming mode, the programming operation will not be performed correctly. Therefore, do not input signals other than the reset signals from the dedicated flash programmer. Figure 18-10. Conflict of Signals (RESET Pin) V850/SB1, V850/SB2 Conflict of signals Dedicated flash programmer connection pin RESET... -
Page 537: Programming Method
CHAPTER 18 FLASH MEMORY 18.6 Programming Method 18.6.1 Flash memory control The following shows the procedure for manipulating the flash memory. Figure 18-11. Procedure for Manipulating Flash Memory Start Supplies RESET pulse Switch to flash memory programming mode Select communication system Manipulate flash memory End? User’s Manual U13850EJ6V0UD... -
Page 538: Flash Memory Programming Mode
FLASH MEMORY 18.6.2 Flash memory programming mode When rewriting the contents of flash memory using the dedicated flash programmer, set the V850/SB1 or V850/SB2 in the flash memory programming mode. When switching modes, set the V pin before releasing reset. -
Page 539: Selection Of Communication Mode
FLASH MEMORY 18.6.3 Selection of communication mode In the V850/SB1 and V850/SB2, the communication mode is selected by inputting pulses (16 pulses max.) to the pin after switching to the flash memory programming mode. The V pulse is generated by the dedicated flash programmer. -
Page 540: Resources Used
CHAPTER 18 FLASH MEMORY The following shows the commands for flash memory control of the V850/SB1 and V850/SB2. All of these commands are issued from the dedicated flash programmer, and the V850/SB1 and V850/SB2 perform the various processing corresponding to the commands. -
Page 541: Chapter 19 Iebus Controller (V850/Sb2)
CHAPTER 19 IEBus CONTROLLER (V850/SB2) IEBus (Inter Equipment Bus) is a small-scale digital data transfer system that transfers data between units. To implement IEBus with the V850/SB2, an external IEBus driver and receiver are necessary because they are not provided. The internal IEBus controller of the V850/SB2 is of negative logic. -
Page 542: Determination Of Bus Mastership (Arbitration)
CHAPTER 19 IEBus CONTROLLER (V850/SB2) 19.1.2 Determination of bus mastership (arbitration) An operation to occupy the bus is performed when a unit connected to the IEBus controls the other units. This operation is called arbitration. When two or more units simultaneously start transmission, arbitration is used to grant one of the units the permission to occupy the bus. -
Page 543: Communication Address
CHAPTER 19 IEBus CONTROLLER (V850/SB2) 19.1.4 Communication address With the IEBus, each unit is assigned a specific 12-bit address. This communication address consists of the following identification numbers: • Higher 4 bits: Group number (number to identify the group to which each unit belongs) •... -
Page 544: Transfer Format Of Iebus
CHAPTER 19 IEBus CONTROLLER (V850/SB2) 19.1.6 Transfer format of IEBus Figure 19-1 shows the transfer signal format of the IEBus. Figure 19-1. IEBus Transfer Signal Format Master Slave Telegraph address address length Header Control field Data field field field field Broad- Master Slave... - Page 545 CHAPTER 19 IEBus CONTROLLER (V850/SB2) (3) Master address field The master address field is output by the master to inform a slave of the master’s address. The configuration of the master address field is as shown in Figure 19-2. If two or more units start transmitting the broadcasting bit at the same time, the master address field makes a judgment of arbitration.
- Page 546 CHAPTER 19 IEBus CONTROLLER (V850/SB2) (4) Slave address field The master outputs the address of the unit with which it is to communicate. Figure 19-3 shows the configuration of the slave address field. A parity bit is output after a 12-bit slave address has been transmitted in order to prevent a wrong slave address from being received by mistake.
- Page 547 CHAPTER 19 IEBus CONTROLLER (V850/SB2) Table 19-2. Contents of Control Bits Note 1 Bit 3 Bit 2 Bit 1 Bit 0 Function Reads slave status Undefined Undefined Note 2 Reads data and locks Note 3 Reads lock address (lower 8 bits) Note 3 Reads lock address (higher 4 bits) Note 2...
- Page 548 CHAPTER 19 IEBus CONTROLLER (V850/SB2) If the control bit received from the master unit is not as shown in Table 19-3, the unit locked by the master unit rejects acknowledging the control bit, and does not output the acknowledge bit. Table 19-3.
- Page 549 Table 19-5. Acknowledge Signal Output Condition of Control Field (a) If received control data is AH, BH, EH, or FH Communication Type Communication Target Lock Status (LOCK) Master Unit Slave Transmission Slave Reception Received Control Data (ALL TRANS) (SLVRQ) Lock = 1 Identification (Match Enable (ENSLVTX) Enable (ENSLVRX)
- Page 550 CHAPTER 19 IEBus CONTROLLER (V850/SB2) (6) Telegraph length field This field is output by the transmission side to inform the reception side of the number of bytes of the transmit data. The configuration of the telegraph length field is as shown in Figure 19-5. Table 19-6 shows the relationship between the telegraph length bit and the number of transmit data.
- Page 551 CHAPTER 19 IEBus CONTROLLER (V850/SB2) (7) Data field This is data output by the transmission side. The master unit transmits or receives data to or from a slave unit by using the data field. The configuration of the data field is as shown below. Figure 19-6.
- Page 552 CHAPTER 19 IEBus CONTROLLER (V850/SB2) The operation differs as follows depending on whether the master transmits or receives data. (a) When master transmits data When the master units writes data to a slave unit, the master unit transmits the data bit and parity bit to the slave unit.
- Page 553 CHAPTER 19 IEBus CONTROLLER (V850/SB2) (9) Acknowledge bit During normal communication (communication from one unit to another), an acknowledge bit is appended to the following locations to check if the data has been correctly received. • End of slave address field •...
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Page 554: Transfer Data
CHAPTER 19 IEBus CONTROLLER (V850/SB2) (c) Last acknowledge bit of telegraph length field The last acknowledge bit of the telegraph length field serves as NACK in any of the following cases, and transmission is stopped. • If the parity of the telegraph length bit is incorrect •... - Page 555 CHAPTER 19 IEBus CONTROLLER (V850/SB2) Figure 19-7. Bit Configuration of Slave Status Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Note 1 Bit 0 Meaning Transmit data is not written in IEBus data register (DR) Transmit data is written in IEBus data register (DR) Note 2 Bit 1...
- Page 556 CHAPTER 19 IEBus CONTROLLER (V850/SB2) (2) Lock address When the lock address is read (control bit: 4H or 5H), the address (12 bits) of the master unit that has issued the lock instruction is configured in 1-byte units as shown below and read. Figure 19-8.
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Page 557: Bit Format
CHAPTER 19 IEBus CONTROLLER (V850/SB2) (c) Lock setting conditions Control Data Broadcasting Communication Individual Communication Communication End Frame End Communication End Frame End Note 3H, 6H Cannot be locked Lock set AH, BH Cannot be locked Cannot be locked Cannot be locked Lock set 0H, 4H, 5H, EH, FH Cannot be locked... -
Page 558: Iebus Controller Configuration
CHAPTER 19 IEBus CONTROLLER (V850/SB2) 19.2 IEBus Controller Configuration The block diagram of the IEBus controller is shown below. Figure 19-10. IEBus Controller Block Diagram CPU interface block BCR(8) UAR(12) SAR(12) PAR(12) CDR(8) DLR(8) DR(8) USR(8) ISR(8) SSR(8) SCR(8) - Page 559 CHAPTER 19 IEBus CONTROLLER (V850/SB2) (a) CPU interface block This is a control block that interfaces between the CPU (V850/SB2) and IEBus. (b) Interrupt control block This control block transfers interrupt request signals from IEBus to the CPU. (c) Internal registers These registers set data to the control registers and fields that control IEBus (for the internal registers, refer to 19.3 Internal Registers of IEBus Controller).
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Page 560: Internal Registers Of Iebus Controller
CHAPTER 19 IEBus CONTROLLER (V850/SB2) 19.3 Internal Registers of IEBus Controller 19.3.1 Internal register list Table 19-7. Internal Registers of IEBus Controller Address Function Register Name Symbol Bit Units for Manipulation After Reset 1 Bit 8 Bits 16 Bits √ √... -
Page 561: Internal Registers
CHAPTER 19 IEBus CONTROLLER (V850/SB2) 19.3.2 Internal registers The internal registers incorporated in the IEBus controller are described below. (1) IEBus control register (BCR) After reset: 00H RW Address: FFFFF3E0H <7> <6> <5> <4> <3> ENIEBUS MSTRQ ALLRQ ENSLVTX ENSLVRX ENIEBUS Communication enable flag IEBus unit stopped... - Page 562 CHAPTER 19 IEBus CONTROLLER (V850/SB2) (a) Communication enable flag (ENIEBUS)...Bit 7 <Set/reset conditions> Set: By software Reset: By software Caution Before setting the ENIBUS flag, make the following setting: • Set the interrupt enabled (EI) status and enable the interrupt processing of INTIE2 (IEBMK = 2).
- Page 563 CHAPTER 19 IEBus CONTROLLER (V850/SB2) (d) Slave transmission enable flag (ENSLVTX)...Bit 4 <Set/reset conditions> Set: By software Reset: By software Cautions 1. Clear the ENSLVTX flag before setting the MSTRQ flag when making a master request. If a slave transmission request is sent in slave mode when the ENSLVTX flag is unset, NACK in the control field will be returned.
- Page 564 CHAPTER 19 IEBus CONTROLLER (V850/SB2) (2) IEBus unit address register (UAR) This register sets the unit address of an IEBus unit. This register must be always set before starting communication. Sets the unit address (12 bits) to bits 11 to 0. 11 10 Address After reset...
- Page 565 CHAPTER 19 IEBus CONTROLLER (V850/SB2) (4) IEBus partner address register (PAR) (a) When slave unit The value of the receive data in the master address field (address of the master unit) is written to this register. If a request “4H” to read the lock address (lower 8 bits) is received from the master, the CPU must read the value of this register, and write it to the lower 8 bits IEBus data register (DR).
- Page 566 CHAPTER 19 IEBus CONTROLLER (V850/SB2) After reset: 01H Address: FFFFF3E8H SELCL2 SELCL1 SELCL0 SELCL2 SELCL1 SELCL0 Function Reads slave status Undefined Undefined Reads data and locks Reads lock address (lower 8 bits) Reads lock address (lower 4 bits) Reads slave status and unlocks Reads data Undefined Undefined...
- Page 567 CHAPTER 19 IEBus CONTROLLER (V850/SB2) (c) Slave status return operation When the IEBus receives a request to transfer from master to slave status or a lock address request (control data: 0H, 6H), whether ACK in the control field is returned or not depends on the status of the IEBus unit.
- Page 568 CHAPTER 19 IEBus CONTROLLER (V850/SB2) Figure 19-12. Interrupt Generation Timing (for (2) and (5)) Control field IEBus sequence Control bits (4 bits) Parity bit (1 bit) ACK bit (1 bit) Terminated by communication error INTIE2 Flag reset by CPU processing Flag set by reception of 0H, 4H, 5H, 6H STATUSF flag...
- Page 569 CHAPTER 19 IEBus CONTROLLER (V850/SB2) Figure 19-14. Timing of INTIE2 Interrupt Generation in Locked State (for (3)) Broad- Start Master address Slave address Control Telegraph length Data IEBus sequence casting (12 + P) (12 + P + A) (4 + P + A) (8 + P + A) (8 + P + A) INTIE2...
- Page 570 CHAPTER 19 IEBus CONTROLLER (V850/SB2) After reset: 01H Address: FFFFF3EAH Setting Remaining number of value communication data bytes 1 byte 2 bytes 32 bytes 255 bytes 256 bytes Cautions 1. If the master issues a request “0H, 4H, 5H, or 6H” to transmit a slave status and lock address (higher 4 bits, lower 8 bits), the contents of this register are set to “01H”...
- Page 571 CHAPTER 19 IEBus CONTROLLER (V850/SB2) (7) IEBus data register (DR) The IEBus data register (DR) sets the communication data. Sets the communication data (8 bits) to bits 7 to Remark The IEBus data register consists of a write register and a read register. Consequently, data written to this register cannot be read as is.
- Page 572 CHAPTER 19 IEBus CONTROLLER (V850/SB2) (8) IEBus unit status register (USR) After reset: 00H Address: FFFFF3EEH <6> <5> <4> <3> <2> SLVRQ ARBIT ALLTRNS LOCK Slave request flag SLVRQ No request from master to slave Request from master to slave Arbitration result flag ARBIT Arbitration win...
- Page 573 CHAPTER 19 IEBus CONTROLLER (V850/SB2) (b) Arbitration result flag (ARBIT)...Bit 5 A flag that indicates the result of arbitration. <Set/reset conditions> Set: When the data output by the IEBus unit during the arbitration period does not match the bus line data. Reset: By the start bit timing.
- Page 574 CHAPTER 19 IEBus CONTROLLER (V850/SB2) (e) Lock status flag (LOCK)...Bit 2 A flag that indicates whether the unit is locked. <Set/reset conditions> Set: When the communication end flag goes low level and the frame end flag goes high level after receipt of a lock specification (3H, 6H, AH, BH) in the control field.
- Page 575 CHAPTER 19 IEBus CONTROLLER (V850/SB2) (9) IEBus interrupt status register (ISR) This register indicates the status when IEBus issues an interrupt. The ISR is read to generate an interrupt, after which the specified interrupt processing is carried out. Reset the ISR register after reading it. Until it is reset, the INTIE2 interrupt signal is not generated (nor held pending).
- Page 576 CHAPTER 19 IEBus CONTROLLER (V850/SB2) After reset: 00H R/W Address: FFFFF3F0H <6> <5> <4> <3> <2> IEERR STARTF STATUSF ENDTRNS ENDFRAM IEERR Communication error flag (during communication) No communication error Communication error STARTF Start interrupt flag Start interrupt does not occur Start interrupt occurs STATUSF Status transmission flag (slave)
- Page 577 CHAPTER 19 IEBus CONTROLLER (V850/SB2) (a) Communication error flag (IEERR)...Bit 6 A flag that indicates the detection of an error during communication. <Set/reset conditions> Set: The flag is set if a timing error, parity error (except in the data field), NACK reception (except in the data field), underrun error, or overrun error (that occurs during broadcasting communication reception) occurs.
- Page 578 CHAPTER 19 IEBus CONTROLLER (V850/SB2) (f) Communication error triggers • Timing error Occurrence conditions: Occurs if the high/low level width of the communication bit has shifted from the prescribed value. Remark: The respective prescribed values are set in the bit processing block and monitored by the internal 8-bit timer.
- Page 579 CHAPTER 19 IEBus CONTROLLER (V850/SB2) (g) Overrun error - supplementary details (i) When the frame ends in the overrun state during individual communication reception If the DR register is not read after entering the overrun state and the retransmitted data reaches the maximum number of bytes (32 bytes), the frame end interrupt (INTIE2) is generated.
- Page 580 CHAPTER 19 IEBus CONTROLLER (V850/SB2) (10)IEBus slave status register (SSR) This register indicates the communication status of the slave unit. After receiving a slave status transmission request from the master, the CPU reads this register, and writes a slave status to the IEBus data register (DR) to transmit the slave status.
- Page 581 CHAPTER 19 IEBus CONTROLLER (V850/SB2) (11)IEBus success count register (SCR) The IEBus success count register (SCR) indicates the number of remaining communication bytes. This register reads the count value of the counter that decrements the value set by the telegraph length register by ACK in the data field.
- Page 582 CHAPTER 19 IEBus CONTROLLER (V850/SB2) (12)IEBus communication count register (CCR) The IEBus communication count register (CCR) indicates the number of remaining bytes in the communication byte number specified in the communication mode. Bits 7 to 0 of the IEBus communication count register (CCR) indicate the number of transfer bytes. This register reads the count value of the counter that is preset to the maximum number of transmitted bytes (32 bytes) per frame specified in mode 1.
- Page 583 CHAPTER 19 IEBus CONTROLLER (V850/SB2) (14)IEBus high-speed clock selection register (IEHCLK) This register selects the clock of IEBus. The main clock frequencies that can be used are shown below. Main clock frequencies other than the following cannot be used. • 6.0 MHz/6.291 MHz •...
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Page 584: Interrupt Operations Of Iebus Controller
CHAPTER 19 IEBus CONTROLLER (V850/SB2) 19.4 Interrupt Operations of IEBus Controller 19.4.1 Interrupt control block Interrupt request signal <1> Communication error IEERR <2> Start interrupt STARTF <3> Status communication STATUSF <4> End of communication ENDTRNS <5> End of frame ENDFRAM <6>... -
Page 585: Interrupt Source List
CHAPTER 19 IEBus CONTROLLER (V850/SB2) 19.4.2 Interrupt source list The interrupt request signals of the internal IEBus controller in the V850/SB2 can be classified into vector interrupts and DMA transfer interrupts. These interrupt request signals can be specified through software manipulation. The interrupt sources are listed below. -
Page 586: Communication Error Source Processing List
CHAPTER 19 IEBus CONTROLLER (V850/SB2) 19.4.3 Communication error source processing list The following table shows the occurrence conditions of the communication errors (timing error, NACK reception error, overrun error, underrun error, and parity error), error processing by the internal IEBus controller, and examples of processing by software. - Page 587 CHAPTER 19 IEBus CONTROLLER (V850/SB2) Table 19-10. Communication Error Source Processing List (2/2) Overrun Error Underrun Error Occurrence Unit status Reception Transmission condition Occurrence DR cannot be read in time before the next DR cannot be written in time before the next condition data is received.
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Page 588: Interrupt Generation Timing And Main Cpu Processing
CHAPTER 19 IEBus CONTROLLER (V850/SB2) 19.5 Interrupt Generation Timing and Main CPU Processing 19.5.1 Master transmission Initial preparation processing: Sets a unit address, slave address, control data, telegraph length, and the first byte of the transmit data. Communication start processing: Sets the bus control register (enables communication, master request, and slave reception). - Page 589 CHAPTER 19 IEBus CONTROLLER (V850/SB2) (1) Slave reception processing If a slave reception request is confirmed during vector interrupt processing, the data transfer direction of macro service must change from RAM (memory) ‘ SFR (peripheral) to SFR (peripheral) ‘ RAM (memory) until the first data is received.
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Page 590: Master Reception
CHAPTER 19 IEBus CONTROLLER (V850/SB2) 19.5.2 Master reception Before performing master reception, it is necessary to notify the slave of slave transmission units. Therefore, more than two communication frames are necessary for master reception. The slave unit prepares the transmit data, set (1) the slave transmission enable flag (ENSLVTX), and waits. Initial preparation processing: Sets a unit address, slave address, and control data. - Page 591 CHAPTER 19 IEBus CONTROLLER (V850/SB2) (1) Interrupt (INTIE1) occurrence If NACK is transmitted (hardware processing) in the data field, an interrupt (INTIE1) is not issued to the CPU, and the same data is retransmitted from the slave. If the receive data is not read in time until the next data is received, the hardware automatically transmits NACK.
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Page 592: Slave Transmission
CHAPTER 19 IEBus CONTROLLER (V850/SB2) 19.5.3 Slave transmission Initial preparation processing: Sets a unit address, telegraph length, and the first byte of the transmit data. Communication start processing: Sets the bus control register (enables communication, slave transmission, and slave reception). Figure 19-19. - Page 593 CHAPTER 19 IEBus CONTROLLER (V850/SB2) (1) Interrupt (INTIE1) occurrence If NACK is received from the master in the data field, an interrupt (INTIE1) is not issued to the CPU, and the same data is retransmitted by hardware. If the transmit data is not written in time during the period of writing the next data, a communication error interrupt occurs due to occurrence of underrun, and communication is abnormally ended.
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Page 594: Slave Reception
CHAPTER 19 IEBus CONTROLLER (V850/SB2) 19.5.4 Slave reception Initial preparation processing: Sets a unit address. Communication start processing: Sets the bus control register (enables communication, disables slave transmission, and enables slave reception). Figure 19-20. Slave Reception µ Approx. 1014 s (mode 1) <1>... - Page 595 CHAPTER 19 IEBus CONTROLLER (V850/SB2) (1) Interrupt (INTIE1) occurrence If NACK is transmitted in the data field, an interrupt (INTIE1) is not issued to the CPU, and the same data is retransmitted from the master. If the receive data is not read in time until the next data is received, NACK is automatically transmitted. (2) Frame end processing The vector interrupt processing in <2>...
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Page 596: Interval Of Occurrence Of Interrupt For Iebus Control
CHAPTER 19 IEBus CONTROLLER (V850/SB2) 19.5.5 Interval of occurrence of interrupt for IEBus control Each control interrupt must occur at each point of communication and perform the necessary processing until the next interrupt occurs. Therefore, the CPU must control the IEBus control block, taking the shortest time of this interrupt into consideration. - Page 597 CHAPTER 19 IEBus CONTROLLER (V850/SB2) (2) Master reception Figure 19-22. Master Reception (Interval of Interrupt Occurrence) Broad- Telegraph Start bit Slave address Control Data Master address casting length Communication starts Communication start interrupt Data Data Data End of communication End of frame Remarks 1.
- Page 598 CHAPTER 19 IEBus CONTROLLER (V850/SB2) (3) Slave transmission Figure 19-23. Slave Transmission (Interval of Interrupt Occurrence) Telegraph Broad- Start bit Master address Slave address Control Data casting length Communication starts Communication Status request start interrupt Data Data Data End of communication End of frame Remarks 1.
- Page 599 CHAPTER 19 IEBus CONTROLLER (V850/SB2) (4) Slave reception Figure 19-24. Slave Reception (Interval of Interrupt Occurrence) Telegraph Broad- Start bit Master address Slave address Control Data casting length Communication starts Communication start interrupt Data Data Data End of communication End of frame Remarks 1.
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Page 600: Chapter 20 Electrical Specifications
CHAPTER 20 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (T = 25°C, V = 0 V) Parameter Symbol Conditions Ratings Unit Supply voltage –0.5 to +7.0 −0.5 to +8.5 Flash memory versions only, Note 1 –0.5 to +7.0 –0.5 to +7.0 –0.5 to +7.0 –0.5 to +0.5 –0.5 to +0.5 –0.5 to +0.5... - Page 601 CHAPTER 20 ELECTRICAL SPECIFICATIONS Notes 1. Make sure that the following conditions of the V voltage application timing are satisfied when the flash memory is written. • • • • When supply voltage rises must exceed V 1 ms or more after V has reached the lower-limit value (4.0 V) of the operating voltage range (see a in the figure below).
- Page 602 4.5 to 5.5 V 4.0 to 5.5 V 4.0 to 5.5 V 4.0 to 5.5 V Note 3 2 to 17 MHz (V850/SB1) 4.0 to 5.5 V 4.5 to 5.5 V 4.0 to 5.5 V 3.0 to 5.5 V 3.0 to 5.5 V 2 to 19 MHz (H versions of V850/SB2) 4.0 to 5.5 V...
- Page 603 • • • • Do not fetch signals from the oscillator. 3. Ensure that the duty of oscillation waveform is between 5.5 and 4.5. 4. Sufficiently evaluate the matching between the V850/SB1 and V850/SB2 devices and the resonator. User’s Manual U13850EJ6V0UD...
- Page 604 The oscillation voltage and oscillation frequency indicate only oscillator characteristics. Use the V850/SB1 and V850/SB2 so that the internal operating conditions are within the specifications of the DC and AC characteristics. User’s Manual U13850EJ6V0UD...
- Page 605 • • • • Do not ground the capacitor to a ground pattern through which a high current flows. • • • • Do not fetch signals from the oscillator. 3. Sufficiently evaluate the matching between the V850/SB1 and V850/SB2 devices and the resonator.
- Page 606 ≤ 5.5 V , EV power supply voltage Normal operation 0.54 (A and B versions of V850/SB2) Normal operation (V850/SB1 and H versions of V850/SB2) µ A Input leakage current, high = BV = EV = AV µ A Input leakage current, low = 0 V –5...
- Page 607 CHAPTER 20 ELECTRICAL SPECIFICATIONS DC Characteristics (T = –40 to +85°C, V = 4.0 to 5.5 V, BV = EV = 3.0 to 5.5 V, AV = 4.5 to 5.5 V (when A/D converter is used), AV = 4.0 to 5.5 V (when A/D converter is not used), = AV = BV = EV...
- Page 608 CHAPTER 20 ELECTRICAL SPECIFICATIONS DC Characteristics (T = –40 to +85°C, V = 4.0 to 5.5 V, BV = EV = 3.0 to 5.5 V, AV = 4.5 to 5.5 V (when A/D converter is used), AV = 4.0 to 5.5 V (when A/D converter is not used), = AV = BV = EV...
- Page 609 CHAPTER 20 ELECTRICAL SPECIFICATIONS DC Characteristics (T = –40 to +85°C, V = 4.0 to 5.5 V, BV = EV = 3.0 to 5.5 V, AV = 4.5 to 5.5 V (when A/D converter is used), AV = 4.0 to 5.5 V (when A/D converter is not used), = AV = BV = EV...
- Page 610 CHAPTER 20 ELECTRICAL SPECIFICATIONS Data Retention Characteristics (T = –40 to +85°C, V = AV = BV = EV = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Note 1 Data retention voltage STOP mode (all functions not operating) DDDR = −40 to +85°C Note 1...
- Page 611 Stop mode release interrupt (NMI, etc.) IHDR (Release by falling edge) Stop mode release interrupt (NMI, etc.) (Release by rising edge) ILDR Note V = 4.0 V indicates the minimum operating voltage of the V850/SB1 and V850/SB2. User’s Manual U13850EJ6V0UD...
- Page 612 CHAPTER 20 ELECTRICAL SPECIFICATIONS AC Characteristics (T = –40 to +85°C, V = 4.0 to 5.5 V, BV = EV = 3.0 to 5.5 V, = 4.5 to 5.5 V (when A/D converter is used), = 4.0 to 5.5 V (when A/D converter is not used), V = AV = BV = EV...
- Page 613 Parameter Symbol Conditions MIN. MAX. Unit 31.2 µ s CLKOUT output cycle <1> V850/SB1 50 ns 31.2 µ s H versions of V850/SB2 52.6 ns 31.2 µ s A and B versions of V850/SB2 76.9 ns CLKOUT high-level width <2>...
- Page 614 CHAPTER 20 ELECTRICAL SPECIFICATIONS (2) Output waveform (other than port 4, port 5, port 6, port 9, and CLKOUT) = –40 to +85° ° ° ° C, V = 4.0 to 5.5 V, BV = EV = 3.0 to 5.5 V, V = BV 0 V) = EV...
- Page 615 CHAPTER 20 ELECTRICAL SPECIFICATIONS (4) Bus timing (a) Clock asynchronous (T = –40 to +85°C, V = BV = 4.0 to 5.5 V, EV = 3.0 to 5.5 V, = AV = BV = EV = 0 V) Parameter Symbol Conditions MIN.
- Page 616 CHAPTER 20 ELECTRICAL SPECIFICATIONS = –40 to +85° ° ° ° C, V (b) Clock asynchronous (T = 4.0 to 5.5 V, BV = 3.0 to 4.0 V, EV = 3.0 to 5.5 V, = AV = BV = EV = 0 V) Parameter Symbol...
- Page 617 CHAPTER 20 ELECTRICAL SPECIFICATIONS (c) Clock synchronous (T = –40 to +85°C, V = BV = 4.0 to 5.5 V, EV = 3.0 to 5.5 V, = AV = BV = EV = 0 V) Parameter Symbol Conditions MIN. MAX. Unit Delay time from CLKOUT↑...
- Page 618 CHAPTER 20 ELECTRICAL SPECIFICATIONS (e) Read cycle (CLKOUT synchronous/asynchronous, 1 wait) CLKOUT (output) <38> A1 to A15 (output) A16 to A21 (output) Note (output) < 42 > < 43 > < 13 > < 39 > Address Data AD0 to AD15 (I/O) <...
- Page 619 CHAPTER 20 ELECTRICAL SPECIFICATIONS (f) Write cycle (CLKOUT synchronous/asynchronous, 1 wait) CLKOUT (output) <38> A1 to A15 (output) A16 to A21 (output) Note (output) < 44 > Address Data AD0 to AD15 (I/O) < 40 > < 10 > < 11 > <...
- Page 620 CHAPTER 20 ELECTRICAL SPECIFICATIONS (g) Bus hold timing CLKOUT (output) < 47 > < 47 > < 48 > <33> HLDRQ (input) < 50 > < 50 > < 37 > < 36 > HLDAK (output) <34> <49> <35> A16 to A21 (output) Note (output) A1 to A15 (output)
- Page 621 CHAPTER 20 ELECTRICAL SPECIFICATIONS (5) Interrupt timing = –40 to +85°C, V = 4.0 to 5.5 V, BV = EV = 3.0 to 5.5 V, V = AV = BV = EV = 0 V) Parameter Symbol Conditions MIN. MAX. Unit NMI high-level width <51>...
- Page 622 CHAPTER 20 ELECTRICAL SPECIFICATIONS (6) RPU timing = –40 to +85°C, V = 4.0 to 5.5 V, BV = EV = 3.0 to 5.5 V, V = AV = BV = EV = 0 V) Parameter Symbol Conditions MIN. MAX. Unit Note TIn0, TIn1 high-level width...
- Page 623 CHAPTER 20 ELECTRICAL SPECIFICATIONS (8) 3-wire serial interface (CSI0 to CSI3) timing (a) Master mode = –40 to +85°C, V = 4.0 to 5.5 V, BV = EV = 3.0 to 5.5 V, V = AV = BV = EV = 0 V) Parameter Symbol...
- Page 624 CHAPTER 20 ELECTRICAL SPECIFICATIONS <62> <63> <64> SCKn (I/O) <65> <66> SIn (input) Input data <67> SOn (output) Output data Remarks 1. The broken lines indicate high impedance. 2. n = 0 to 3 User’s Manual U13850EJ6V0UD...
- Page 625 CHAPTER 20 ELECTRICAL SPECIFICATIONS (9) 3-wire variable length serial interface (CSI4) timing (a) Master mode = –40 to +85° ° ° ° C, V = 4.0 to 5.5 V, BV = EV = 3.0 to 5.5 V, V = AV = BV = EV = 0 V)
- Page 626 CHAPTER 20 ELECTRICAL SPECIFICATIONS <68> <69> <70> SCK4 (I/O) <71> <72> SI4 (input) Input data <73> SO4 (output) Output data Remark The broken lines indicate high impedance. User’s Manual U13850EJ6V0UD...
- Page 627 CHAPTER 20 ELECTRICAL SPECIFICATIONS (10) I C bus mode (Y versions only) (1/2) = –40 to +85°C, V = 4.0 to 5.5 V, BV = EV = 3.0 to 5.5 V, V = AV = BV = EV = 0 V) Parameter Symbol Normal Mode...
- Page 628 CHAPTER 20 ELECTRICAL SPECIFICATIONS (10) I C bus mode (Y versions only) (2/2) <76> <77> SCLn (I/O) <78> <82> <81> <79> <80> <75> <84> <83> <75> SDAn (I/O) <74> <81> <82> Stop Start Restart Stop condition condition condition condition Remark n = 0, 1 A/D Converter Characteristics (T = –40 to +85°C, V = AV...
- Page 629 CHAPTER 20 ELECTRICAL SPECIFICATIONS = –40 to +85° ° ° ° C, V IEBus Controller Characteristics (V850/SB2 only) (T = 4.0 to 5.5 V, = EV = 3.0 to 5.5 V, V = AV = BV = EV = 0 V) Parameter Symbol Conditions...
- Page 630 CHAPTER 20 ELECTRICAL SPECIFICATIONS Flash Memory Programming Mode (1) µ µ µ µ PD70F3030B, 70F3030BY, 70F3032A, 70F3032AY, 70F3032B, 70F3032BY, 70F3033B, 70F3033BY = − − − − 20 to 85° ° ° ° C, V Write/erase characteristics (T = AV = BV = EV = 4.5 to 5.5 V, = AV...
- Page 631 CHAPTER 20 ELECTRICAL SPECIFICATIONS (2) µ µ µ µ PD70F3033A, 70F3033AY = 10 to 85° ° ° ° C Write/erase characteristics (T … K rank product, = − − − − 20 to +85° ° ° ° C … E rank product, = AV = BV = EV...
- Page 632 CHAPTER 20 ELECTRICAL SPECIFICATIONS (3) µ µ µ µ PD70F3035A, 70F3035AY = 10 to 85° ° ° ° C Write/erase characteristics (T … K, E rank product, = − − − − 20 to +85° ° ° ° C … P rank product, = AV = BV = EV...
- Page 633 CHAPTER 20 ELECTRICAL SPECIFICATIONS (4) µ µ µ µ PD70F3035B, 70F3035BY, 70F3037A, 70F3037AY, = − − − − 20 to +85° ° ° ° C, V Write/erase characteristics (T = AV = BV = EV = 4.5 to 5.5 V, = AV = BV = EV...
- Page 634 CHAPTER 20 ELECTRICAL SPECIFICATIONS (5) µ µ µ µ PD70F3036H, 70F3036HY, 70F3037H, 70F3037HY = − − − − 20 to +85° ° ° ° C, V Write/erase characteristics (T = AV = BV = EV = 4.5 to 5.5 V, = AV = BV = EV...
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Page 635: Chapter 21 Package Drawings
CHAPTER 21 PACKAGE DRAWINGS 100-PIN PLASTIC LQFP (FINE PITCH) (14x14) detail of lead end NOTE ITEM MILLIMETERS Each lead centerline is located within 0.08 mm of 16.00±0.20 its true position (T.P.) at maximum material condition. 14.00±0.20 14.00±0.20 16.00±0.20 1.00 1.00 0.22 +0.05 −0.04 0.08... - Page 636 CHAPTER 21 PACKAGE DRAWINGS 100-PIN PLASTIC QFP (14x20) detail of lead end NOTE ITEM MILLIMETERS Each lead centerline is located within 0.15 mm of 23.6±0.4 its true position (T.P.) at maximum material condition. 20.0±0.2 14.0±0.2 17.6±0.4 0.30±0.10 0.15 0.65 (T.P.) 1.8±0.2 0.8±0.2 0.15 +0.10...
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Page 637: Chapter 22 Recommended Soldering Conditions
CHAPTER 22 RECOMMENDED SOLDERING CONDITIONS The V850/SB1 and V850/SB2 should be soldered and mounted under the following recommended conditions. For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales representative. - Page 638 CHAPTER 22 RECOMMENDED SOLDERING CONDITIONS Table 22-1. Surface Mounting Type Soldering Conditions (2/5) (2) µ µ µ µ PD703030BGC-xxx-8EU: 100-pin plastic LQFP (fine pitch) (14 × × × × 14) µ µ µ µ PD703030BYGC-xxx-8EU: 100-pin plastic LQFP (fine pitch) (14 × × × × 14) µ...
- Page 639 CHAPTER 22 RECOMMENDED SOLDERING CONDITIONS Table 22-1. Surface Mounting Type Soldering Conditions (3/5) µ µ µ µ PD703030BGF-xxx-3BA: µ µ µ µ PD703035AGF-xxx-3BA: 100-pin plastic QFP (14 × × × × 20) 100-pin plastic QFP (14 × × × × 20) µ...
- Page 640 CHAPTER 22 RECOMMENDED SOLDERING CONDITIONS Table 22-1. Surface Mounting Type Soldering Conditions (4/5) (4) µ µ µ µ PD70F3030BGF-3BA: 100-pin plastic QFP (14 × × × × 20) µ µ µ µ PD70F3030BYGF-3BA: 100-pin plastic QFP (14 × × × × 20) µ...
- Page 641 CHAPTER 22 RECOMMENDED SOLDERING CONDITIONS Table 22-1. Surface Mounting Type Soldering Conditions (5/5) (5) µ PD70F3030BGC-8EU: 100-pin plastic LQFP (fine pitch) (14 × × × × 14) µ PD70F3030BYGC-8EU: 100-pin plastic LQFP (fine pitch) (14 × × × × 14) µ...
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Page 642: Appendix Anotes On Target System Design
APPENDIX A NOTES ON TARGET SYSTEM DESIGN The following shows a diagram of the connection conditions between the in-circuit emulator option board and conversion connector. Design your system making allowances for conditions such as the shape of parts mounted on the target system as shown below. - Page 643 APPENDIX A NOTES ON TARGET SYSTEM DESIGN Figure A-2. 100-Pin Plastic QFP (14 × × × × 20) Side view In-circuit emulator IE-703002-MC In-circuit emulator option board IE-703037-MC-EM1 Conversion connector 178 mm Note NEXB-100-SD/RB YQGUIDE YQPACK100RB NQPACK100RB Target system Note YQSOCKET100SDN (included with IE-703002-MC) to this portion for adjusting the height (height: 3.2 mm). Top view IE-703002-MC Target system...
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Page 644: Appendix Bregister Index
APPENDIX B REGISTER INDEX (1/7) Symbol Name Unit Page ADCR A/D conversion result register ADCRH A/D conversion result register H ADIC Interrupt control register INTC 162 to 164 ADM1 A/D converter mode register 1 ADM2 A/D converter mode register 2 Analog input channel specification register ASIM0 Asynchronous serial interface mode register 0... - Page 645 APPENDIX B REGISTER INDEX (2/7) Symbol Name Unit Page CR40 8-bit compare register 4 Timer CR45 16-bit compare register 45 (when TM4 and TM5 are connected in cascade) Timer CR50 8-bit compare register 5 Timer CR60 8-bit compare register 6 Timer CR67 16-bit compare register 67 (when TM6 and TM7 are connected in cascade)
- Page 646 APPENDIX B REGISTER INDEX (3/7) Symbol Name Unit Page DIOA3 DMA peripheral I/O address register 3 DMAC DIOA4 DMA peripheral I/O address register 4 DMAC DIOA5 DMA peripheral I/O address register 5 DMAC IEBus telegraph length register IEBus DMAIC0 Interrupt control register INTC 162 to 164 DMAIC1...
- Page 647 APPENDIX B REGISTER INDEX (4/7) Symbol Name Unit Page IICF0 IIC flag register 0 IICF1 IIC flag register 1 IICIC1 Interrupt control register 160 to 164 IICS0 IIC status register 0 285, 344 IICS1 IIC status register 1 285, 344 IICX0 IIC function expansion register 0 289, 350...
- Page 648 APPENDIX B REGISTER INDEX (5/7) Symbol Name Unit Page PIC4 Interrupt control register INYC 162 to 164 PIC5 Interrupt control register INTC 162 to 164 PIC6 Interrupt control register INTC 162 to 164 Port 0 mode register Port Port 1 mode register Port Port 2 mode register Port...
- Page 649 APPENDIX B REGISTER INDEX (6/7) Symbol Name Unit Page SIO0 Serial I/O shift register 0 SIO1 Serial I/O shift register 1 SIO2 Serial I/O shift register 2 SIO3 Serial I/O shift register 3 SIO4 Variable-length serial I/O shift register 4 IEBus slave status register IEBus STIC0...
- Page 650 APPENDIX B REGISTER INDEX (7/7) Symbol Name Unit Page TMC3 8-bit timer mode control register 3 Timer TMC4 8-bit timer mode control register 4 Timer TMC5 8-bit timer mode control register 5 Timer TMC6 8-bit timer mode control register 6 Timer TMC7 8-bit timer mode control register 7...
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Page 651: Appendix Cinstruction Set List
APPENDIX C INSTRUCTION SET LIST • How to Read Instruction Set List This column shows instruction groups. Instructions are divided into each instruction group and described. This column shows instruction mnemonics. This column shows instruction operands (refer to Table C-1). This column shows instruction codes (opcode) in binary format. - Page 652 APPENDIX C INSTRUCTION SET LIST Table C-2. Symbols Used for Opcode Symbol Description 1-bit data of code that specifies reg1 or regID 1-bit data of code that specifies reg2 1-bit data of displacement 1-bit data of immediate data cccc 4-bit data that indicates condition code 3-bit data that specifies bit number Table C-3.
- Page 653 APPENDIX C INSTRUCTION SET LIST Table C-4. Symbols Used for Flag Operation Symbol Description (blank) Not affected Cleared to 0 × Set of cleared according to result Previously saved value is restored Table C-5. Condition Codes Condition Name (cond) Condition Code (cccc) Conditional Expression Description 0000...
- Page 654 APPENDIX C INSTRUCTION SET LIST Instruction Set List (1/4) Mnemonic Operand Opcode Operation Flag Instruction Group CY OV S Z SAT adr ← ep + zero-extend (disp7) Load/store SLD.B disp7 [ep], rrrrr0110ddddddd GR [reg2] ← sign-extend (Load-memory reg2 (adr, Byte)) adr ←...
- Page 655 APPENDIX C INSTRUCTION SET LIST Instruction Set List (2/4) Mnemonic Operand Opcode Operation Flag Instruction Group CY OV S Z SAT GR [reg2] ← GR [reg2] + GR [reg1] × × × × Arithmetic reg1, reg2 rrrrr001110RRRRR operation GR [reg2] ← GR [reg2] + sign-extend ×...
- Page 656 APPENDIX C INSTRUCTION SET LIST Instruction Set List (3/4) Operand Opcode Mnemonic Operation Flag Instruction Group CY OV S Z SAT GR [reg2] ← GR [reg2] XOR GR [reg1] × × Logic reg1, reg2 rrrrr001001RRRRR operation GR [reg2] ← GR [reg1] XOR zero-extend ×...
- Page 657 APPENDIX C INSTRUCTION SET LIST Instruction Set List (4/4) Mnemonic Operand Opcode Operation Flag Instruction Group CY OV S Z SAT SR [regID] ←GR Special LDSR reg2, regID rrrrr111111RRRRR regID = EIPC, FEPC 0000000000100000 [reg2] regID = EIPSW, (Note) FEPSW ×...
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Page 658: Appendix Dindex
APPENDIX D INDEX [Number] ANI0 to ANI11 ------------------------------------------------ 86 16-bit capture/compare register n0 -------------------- 203 Arbitration ---------------------------------------------------- 319 16-bit capture/compare register n1 -------------------- 204 ASCK0 --------------------------------------------------------- 82 16-bit compare register 23 ------------------------------- 250 ASCK1 --------------------------------------------------------- 83 16-bit compare register 45 ------------------------------- 250 ASIM0, ASIM1 ---------------------------------------------- 402 16-bit compare register 67 ------------------------------- 250 ASIS0, ASIS1 ----------------------------------------------- 403... - Page 659 APPENDIX D INDEX CCR ----------------------------------------------------------- 582 DMA transfer request control block --------------------452 CDR ----------------------------------------------------------- 565 DMAIC0 to DMAIC5 ----------------------------- 162 to 164 CG ---------------------------------------------------------- 40, 51 DMA start factor expansion register -------------------459 Channel control block ------------------------------------- 452 DMAS ---------------------------------------------------------459 CLKOUT ------------------------------------------------------- 90 DR --------------------------------------------------------------571 Clock generation function ------------------------------- 182 DRA0 to DRA5 ----------------------------------------------454...
- Page 660 APPENDIX D INDEX C bus mode ------------------------------------------------ 275 Internal ROM area ----------------------------------------- 107 C interrupt request --------------------------------------- 299 Interrupt control register ------------------------ 162 to 164 IC -----------------------------------------------------------------91 Interrupt controller -------------------------------------- 40, 50 ID flag ---------------------------------------------------------- 165 Interrupt request signal generator --------------------- 279 IDLE mode -------------------------------------------- 188, 192 Interrupt source register ----------------------------------- 99 Idle state insertion function ------------------------------ 134...
- Page 661 APPENDIX D INDEX Oscillation stabilization time ---------------------------- 196 PM3 ------------------------------------------------------------489 Oscillation stabilization time PM4 ------------------------------------------------------------493 selection register ----------------------------- 187, 262, 267 PM5 ------------------------------------------------------------493 OSTS -------------------------------------------- 187, 262, 267 PM6 ------------------------------------------------------------496 Overall error ------------------------------------------------- 447 PM9 ------------------------------------------------------------501 Port -------------------------------------------------------- 42, 52 Port 0 ----------------------------------------------------------474 P0 -------------------------------------------------------------- 474 Port 0 mode register ---------------------------------------476...
- Page 662 APPENDIX D INDEX PSC ------------------------------------------------------------ 186 RXB0, RXB1 ------------------------------------------------ 400 PSW ----------------------------------------------------------- 100 RXD0 ----------------------------------------------------------- 82 PU0 ------------------------------------------------------------ 476 RXD1 ----------------------------------------------------------- 83 PU1 ------------------------------------------------------------ 480 PU10 ---------------------------------------------------------- 505 PU11 ---------------------------------------------------------- 509 Sampling time ----------------------------------------------- 450 PU2 ------------------------------------------------------------ 485 SAR -----------------------------------------------------433, 564 PU3 ------------------------------------------------------------ 489 SCK0, SCK1 -------------------------------------------------- 82 Pull-up resistor option register 0 ----------------------- 476...
- Page 663 X1 --------------------------------------------------------------- 90 USR ----------------------------------------------------------- 572 X2 --------------------------------------------------------------- 90 XT1 ------------------------------------------------------------- 90 XT2 ------------------------------------------------------------- 90 V850/SB1 ------------------------------------------------- 33, 43 V850/SB2 ------------------------------------------------- 53, 63 Variable-length serial control register 4 -------------- 422 Zero-scale error ---------------------------------------------448 Variable-length serial I/O shift register 4 ------------- 420 Variable-length serial setting register 4 -------------- 423 User’s Manual U13850EJ6V0UD...
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Page 664: Appendix Erevision History
(1/5) Edition Major Revisions from Previous Edition Applied to: Modification of 1.2.3 Ordering information (V850/SB1) CHAPTER 1 INTRODUCTION Modification of 1.3.3 Ordering information (V850/SB2) Modification of description in 2.3 (5) P40 to P47 (Port 4) - Page 665 FUNCTIONS Modification of description and addition of Note in 3.2.2 (2) Program status word (PSW) Addition of 3.4.5 (2) (a) V850/SB1 (uPD703031B, 703031BY), V850/SB2 ( µ µ µ µ PD703034B, 703034BY) Modification of Note and addition of registers in 3.4.8 Peripheral I/O registers Addition of description in 3.4.9 Specific registers...
- Page 666 APPENDIX E REVISION HISTORY (3/5) Edition Major Revisions from Previous Edition Applied to: Modification of description in Table 6-3 Operating Statuses in Software STOP Mode CHAPTER 6 CLOCK GENERATION Addition of 6.6 (1) While an instruction is being executed on internal ROM FUNCTION Addition of 6.6 (2) While an instruction is being executed on external ROM Addition of description in Caution in 7.1.4 (1) 16-bit timer mode control registers 0, 1...
- Page 667 CHAPTER 12 DMA FUNCTIONS Addition of 12.4 (2) (a) V850/SB1 ( µ µ µ µ PD703031B, 703031BY), V850/SB2 ( µ µ µ µ PD703034B, 703034BY) Addition of Caution in 12.4 (5) DMA channel control registers 0 to 5 (DCHC0 to DCHC5) Addition of 12.5 Operation...
- Page 668 APPENDIX E REVISION HISTORY (5/5) Edition Major Revisions from Previous Edition Applied to: Modification of description in Table 19-5 Acknowledge Signal Output Condition of CHAPTER 19 IEBus Control Field CONTROLLER (V850/SB2) Addition of register to Table 19-7 Internal Registers of IEBus Controller Addition of Remark in 19.3.2 (13) IEBus clock selection register (IECLK) Addition of 19.3.2 (14) IEBus high-speed clock selection register (IEHCLK) Addition of CHAPTER 20 ELECTRICAL SPECIFICATIONS...