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5.6.2
External wait function
To synchronize an extremely slow external device, I/O, or asynchronous system, any number of wait states can be
inserted in the bus cycle by using the external wait pin (WAIT).
Access to each area of the internal ROM, internal RAM, and internal peripheral I/O is not subject to control by the
external wait function, in the same manner as the programmable wait function.
The WAIT signal can be input asynchronously to CLKOUT, and is sampled at the falling edge of the clock in the T2
and TW states of the bus cycle in the multiplexed bus mode. In the separate bus mode, it is sampled at the rising
edge of the clock immediately after the T1 and TW states of the bus cycle. If the setup/hold time of the sampling
timing is not satisfied, a wait state is inserted in the next state, or not inserted at all.
5.6.3
Relationship between programmable wait and external wait
Wait cycles are inserted as the result of an OR operation between the wait cycles specified by the set value of the
programmable wait and the wait cycles controlled by the WAIT pin. In other words, the number of wait cycles is
determined by the side with the greatest number of cycles.
For example, if the timing of the programmable wait and the WAIT pin signal is as illustrated below, three wait
states will be inserted in the bus cycle.
Figure 5-3. Example of Inserting Wait States in Separate Bus Mode
CLKOUT
WAIT pin
Wait via WAIT pin
Programmable wait
Wait control
Remark
The circles indicate the sampling timing.
CHAPTER 5 BUS CONTROL FUNCTION
Programmable wait
Wait via WAIT pin
T1
Preliminary User's Manual U15905EJ1V0UD
Wait control
TW
TW
TW
T2
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