Wait Signal - NEC V850/SA1 mPD703015 Preliminary User's Manual

32-/16-bit single-chip microcontrollers
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(6)

Wait signal

The wait signal (WAIT) is used to notify the communication partner that a device (master or slave) is preparing
to transmit or receive data (i.e., is in a wait state).
Setting the SCL pin to low level notifies the communication partner of the wait status. When wait status has
been canceled for both the master and slave devices, the next data transfer can begin.
(1) When master device has a nine-clock wait and slave device has an eight-clock wait
Master
IIC0
SCL
Slave
IIC0
SCL
ACKE
Transfer lines
SCL
SDA
238
CHAPTER 10 SERIAL INTERFACE FUNCTION
Figure 10-19. Wait Signal (1/2)
(master transmits, slave receives, and ACKE = 1)
Master returns to high
impedance but slave
is in wait state (low level).
6
7
8
9
Wait after output
of eighth clock.
H
6
7
8
D2
D1
D0
Wait after output
of ninth clock.
IIC0 data write (cancel wait)
1
FFH is written to IIC0 or WREL is set to 1.
9
1
ACK
D7
2
3
2
3
D6
D5

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