NEC V850/SB1TM User Manual

32-bit single-chip microcontroller

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User's Manual

V850/SB1

32-Bit Single-Chip Microcontroller

Hardware

µ µ µ µ PD703030A

µ µ µ µ PD703030AY

µ µ µ µ PD703031A

µ µ µ µ PD703031AY

µ µ µ µ PD703032A

µ µ µ µ PD703032AY

µ µ µ µ PD703033A

µ µ µ µ PD703033AY

µ µ µ µ PD70F3032A

µ µ µ µ PD70F3032AY

µ µ µ µ PD70F3033A

µ µ µ µ PD70F3033AY

Document No. U13850EJ4V0UM00 (4th edition)

Date Published April 2001 N CP(K)

1999, 2000

1998

Printed in Japan

, V850/SB2

µ µ µ µ PD703034A

µ µ µ µ PD703034AY

µ µ µ µ PD703035A

µ µ µ µ PD703035AY

µ µ µ µ PD703036A

µ µ µ µ PD703036AY

µ µ µ µ PD703037A

µ µ µ µ PD703037AY

µ µ µ µ PD70F3035A

µ µ µ µ PD70F3035AY

µ µ µ µ PD70F3037A

µ µ µ µ PD70F3037AY

Table of Contents

Summary of Contents for NEC V850/SB1TM

Page 1 User’s Manual V850/SB1 , V850/SB2 32-Bit Single-Chip Microcontroller Hardware µ µ µ µ PD703030A µ µ µ µ PD703034A µ µ µ µ PD703030AY µ µ µ µ PD703034AY µ µ µ µ PD703031A µ µ µ µ PD703035A µ µ µ µ PD703031AY µ...
Page 2 [MEMO] User’s Manual U13850EJ4V0UM...
Page 3 The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
Page 4 NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others.
Page 5 Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: •...
Page 6 Major Revisions in This Edition Page Description p. 33 Modification of 1.2.3 Ordering information (V850/SB1) Modification of 1.3.3 Ordering information (V850/SB2) p. 43 p. 62 Modification of description in 2.3 (5) P40 to P47 (Port 4) Modification of description in 2.3 (6) P50 to P57 (Port 5) p.
Page 7 INTRODUCTION Readers This manual is intended for users who wish to understand the functions of the V850/SB1 and V850/SB2 and design application systems using the V850/SB1 or V850/SB2. Purpose This manual is intended to give users to an understanding of the hardware functions described in the Organization below.
Page 8 Conventions Data significance: Higher digits on the left and lower digits on the right Active low: xxx (overscore over pin or signal name) Memory map address: Higher addresses at the top and lower addresses at the bottom Note: Footnote for items marked with Note in the text Caution: Information requiring particular attention Remark: Supplementary information Number representation: Binary …...
Page 9 Related documents for development tool (user’s manual) Document Name Document No. IE-703002-MC (In-Circuit Emulator) U11595E IE-703037-MC-EM1 (In-Circuit Emulator Option Board) U14151E CA850 (Ver. 2.30 or Later) (C Compiler Operation U14568E Package) C Language U14566E Assembly Language U14567E Project Manager U14569E ID850 (Ver.
Page 10: Table Of Contents
CONTENTS CHAPTER 1 INTRODUCTION ......................29 General ..........................29 V850/SB1 ..........................31 1.2.1 Features (V850/SB1) .......................31 1.2.2 Application fields (V850/SB1) ....................32 1.2.3 Ordering information (V850/SB1).....................33 1.2.4 Pin configuration (top view) (V850/SB1) ..................34 1.2.5 Function blocks (V850/SB1) ....................37 V850/SB2 ..........................41 1.3.1 Features (V850/SB2) .......................41 1.3.2...
Page 11 4.2.2 Control register ........................107 Bus Access ......................... 107 4.3.1 Number of access clocks....................... 107 4.3.2 Bus width ..........................108 Memory Block Function..................... 109 Wait Function........................110 4.5.1 Programmable wait function ....................110 4.5.2 External wait function......................111 4.5.3 Relationship between programmable wait and external wait..........111 Idle State Insertion Function .....................
Page 12 Priority Control ........................151 5.6.1 Priorities of interrupts and exceptions..................151 5.6.2 Multiple interrupt servicing .....................151 Interrupt Latency Time ....................... 154 Periods Where Interrupt Is Not Acknowledged ............... 154 Key Interrupt Function ....................... 156 CHAPTER 6 CLOCK GENERATION FUNCTION ................ 158 Outline ..........................
Page 13 CHAPTER 8 WATCH TIMER ......................230 Function ..........................230 Configuration........................231 Watch Timer Control Register................... 232 Operation..........................234 8.4.1 Operation as watch timer....................... 234 8.4.2 Operation as interval timer..................... 234 8.4.3 Cautions..........................235 CHAPTER 9 WATCHDOG TIMER....................236 Functions ..........................236 Configuration ........................
Page 14 10.5.2 CSI4 control registers ......................335 10.5.3 Operations ..........................339 CHAPTER 11 A/D CONVERTER ....................344 11.1 Function..........................344 11.2 Configuration ........................346 11.3 Control Registers........................ 348 11.4 Operation..........................351 11.4.1 Basic operation ........................351 11.4.2 Input voltage and conversion result ..................353 11.4.3 A/D converter operation mode ....................354 11.5 Low Power Consumption Mode..................
Page 15 CHAPTER 15 RESET FUNCTION ....................416 15.1 General ..........................416 15.2 Pin Operations ........................416 CHAPTER 16 REGULATOR......................417 16.1 Outline ..........................417 16.2 Operation..........................417 CHAPTER 17 ROM CORRECTION FUNCTION ................418 17.1 General ..........................418 17.2 ROM Correction Peripheral I/O Registers ................ 419 17.2.1 Correction control register (CORCN) ..................
Page 16 19.2 IEBus Controller Configuration..................453 19.3 Internal Registers of IEBus Controller ................455 19.3.1 Internal register list ........................455 19.3.2 Internal registers........................456 19.4 Interrupt Operations of IEBus Controller ................. 478 19.4.1 Interrupt control block ......................478 19.4.2 Interrupt source list........................479 19.4.3 Communication error source processing list ................480 19.5 Interrupt Generation Timing and Main CPU Processing ..........
Page 17 LIST OF FIGURES (1/9) Figure No. Title Page CPU Register Set ............................74 Program Counter (PC).............................75 Interrupt Source Register (ECR)........................76 Program Status Word (PSW) ..........................77 CPU Address Space............................79 Image on Address Space ..........................80 Program Space..............................81 Data Space ..............................81 Memory Map ..............................82 3-10 Internal ROM Area (128 KB)..........................83 3-11...
Page 18 LIST OF FIGURES (2/9) Figure No. Title Page Non-Maskable Interrupt Servicing......................... 128 Acknowledging Non-Maskable Interrupt Request ..................129 RETI Instruction Processing ......................... 130 NP Flag (NP)..............................131 Rising Edge Specification Register 0 (EGP0) Format .................. 132 Falling Edge Specification Register 0 (EGN0) Format.................. 132 Maskable Interrupt Servicing ........................
Page 19 LIST OF FIGURES (3/9) Figure No. Title Page 7-10 Configuration of Interval Timer ........................188 7-11 Timing of Interval Timer Operation ........................188 7-12 Control Register Settings in PPG Output Operation..................189 7-13 Control Register Settings for Pulse Width Measurement with Free-Running Counter and One Capture Register .................................190 7-14 Configuration for Pulse Width Measurement with-Free Running Counter.............191...
Page 20 LIST OF FIGURES (4/9) Figure No. Title Page 7-46 Cascade Connection Mode with 16-Bit Resolution ..................228 7-47 Start Timing of Timer n ..........................229 7-48 Timing After Compare Register Changes During Timer Count Operation ............ 229 Block Diagram of Watch Timer ........................230 Watch Timer Mode Control Register (WTNM) ....................
Page 21 LIST OF FIGURES (5/9) Figure No. Title Page 10-25 Communication Reservation Timing......................300 10-26 Timing for Accepting Communication Reservations ..................300 10-27 Communication Reservation Flow Chart .......................301 10-28 Master Operation Flow Chart.........................303 10-29 Slave Operation Flow Chart...........................304 10-30 Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) .306 10-31 Example of Slave to Master Communication (When 9-Clock Wait Is Selected for Both Master and Slave) .309 10-32...
Page 22 LIST OF FIGURES (6/9) Figure No. Title Page 11-6 Relationship Between Analog Input Voltage and A/D Conversion Result............. 353 11-7 A/D Conversion by Hardware Start (with Falling Edge Specified) ..............354 11-8 A/D Conversion by Software Start ........................ 355 11-9 Handling of Analog Input Pin ........................
Page 23 LIST OF FIGURES (7/9) Figure No. Title Page 14-18 Block Diagram of P23, P26, and P27 ......................388 14-19 Port 3 (P3) ..............................389 14-20 Port 3 Mode Register (PM3) ..........................390 14-21 Pull-Up Resistor Option Register 3 (PU3) .....................390 14-22 Port 3 Function Register (PF3) ........................391 14-23 Block Diagram of P30 to P32 and P35 to P37....................391 14-24...
Page 24 LIST OF FIGURES (8/9) Figure No. Title Page 18-1 Environment Required for Writing Programs to Flash Memory ..............425 18-2 Communication with Dedicated Flash Programmer (UART0)............... 425 18-3 Communication with Dedicated Flash Programmer (CSI0) ................426 Communication with Dedicated Flash Programmer (CSI0 + HS) ..............426 18-4 18-5 Pin Connection Example ........................
Page 25 LIST OF FIGURES (9/9) Figure No. Title Page 19-29 Configuration of Interrupt Control Block......................478 19-30 Master Transmission .............................482 19-31 Master Reception............................484 19-32 Slave Transmission ............................486 19-33 Slave Reception.............................488 19-34 Master Transmission (Interval of Interrupt Occurrence) ................490 19-35 Master Reception (Interval of Interrupt Occurrence) ..................491 19-36 Slave Transmission (Interval of Interrupt Occurrence) ..................492 19-37...
Page 26 LIST OF TABLES (1/3) Table No. Title Page Product Lineup of V850/SB1 and V850/SB2 ....................30 Pin I/O Buffer Power Supply ........................... 51 Differences of Pins Between V850/SB1 and V850/SB2.................. 51 Pin Operating State in Operation Mode ......................58 Program Registers ............................75 System Register Numbers ..........................
Page 27 LIST OF TABLES (2/3) Table No. Title Page 10-1 Configuration of CSIn ............................245 10-2 Configuration of I Cn .............................255 10-3 Selection Clock Setting..........................267 10-4 INTIICn Generation Timing and Wait Control ....................294 10-5 Extension Code Bit Definitions ........................296 10-6 Status During Arbitration and Interrupt Request Generation Timing .............297 10-7 Wait Periods ..............................299 10-8...
Page 28 LIST OF TABLES (3/3) Table No. Title Page 19-1 Transfer Rate and Maximum Number of Transfer Bytes in Communication Mode 1........437 19-2 Contents of Control Bits ..........................442 19-3 Control Field for Locked Slave Unit ......................443 19-4 Control Field for Unlocked Slave Unit ......................443 19-5 Acknowledge Signal Output Condition of Control Field ................
Page 29: Chapter 1 Introduction
CHAPTER 1 INTRODUCTION The V850/SB1 and V850/SB2 are products in NEC’s V850 Family of single-chip microcontrollers designed for low power operation. 1.1 General The V850/SB1 and V850/SB2 are 32-bit single-chip microcontrollers that include the V850 Family’s CPU core, and peripheral functions such as ROM/RAM, a timer/counter, a serial interface, an A/D converter, a timer, and DMA controller.
Page 30 CHAPTER 1 INTRODUCTION Table 1-1. Product Lineup of V850/SB1 and V850/SB2 Product Name On-Chip Package On-Chip Size IEBus Commercial Part Number Type Size Name µ PD703031A V850/SB1 None Mask ROM 128 KB 12 KB 100-pin QFP (14 × 20) None /100-pin LQFP (14 ×...
Page 31: V850/Sb1
CHAPTER 1 INTRODUCTION 1.2 V850/SB1 1.2.1 Features (V850/SB1) Number of instructions: 74 Minimum instruction execution time 50 ns (operating at 20 MHz, external power supply 5 V, regulator output 3.3 V) 32 bits × 32 registers General-purpose registers Signed multiplication (16 × 16 → 32): 100 ns (operating at 20 MHz) Instruction set (able to execute instructions in parallel continuously without creating any register hazards).
Page 32: Application Fields (V850/Sb1)
CHAPTER 1 INTRODUCTION Serial interface (SIO) Asynchronous serial interface (UART) Clocked serial interface (CSI) C) (only for µ PD703030AY, 703031AY, 703032AY, 703033AY, C bus interface (I 70F3032AY, and 70F3033AY) 8-/16-bit variable-length serial interface CSI/UART: 2 channels CSI/I 2 channels CSI (8-/16-bit valuable): 1 channel Dedicated baud rate generator: 3 channels A/D converter...
Page 33: Ordering Information (V850/Sb1)
CHAPTER 1 INTRODUCTION 1.2.3 Ordering information (V850/SB1) Part Number Package Internal ROM µ PD703031AGC-xxx-8EU 100-pin plastic LQFP (fine pitch) (14 × 14) Mask ROM (128 KB) µ PD703031AGF-xxx-3BA 100-pin plastic QFP (14 × 20) Mask ROM (128 KB) µ PD703031AYGC-xxx-8EU 100-pin plastic LQFP (fine pitch) (14 ×...
Page 34: Pin Configuration (Top View) (V850/Sb1)
CHAPTER 1 INTRODUCTION 1.2.4 Pin configuration (top view) (V850/SB1) 100-pin plastic LQFP (fine pitch) (14 × 14) • µ PD703031AGC-xxx-8EU • µ PD70F3033AGC-8EU • µ PD703031AYGC-xxx-8EU • µ PD70F3033AYGC-8EU • µ PD703033AGC-xxx-8EU • µ PD703033AYGC-xxx-8EU P21/SO2 P71/ANI1 Note 2 P70/ANI0 P22/SCK2/SCL1 P23/RXD1/SI3 P24/TXD1/SO3...
Page 35 CHAPTER 1 INTRODUCTION 100-pin plastic QFP (14 × 20) • µ PD703030AGF-xxx-3BA • µ PD703032AGF-xxx-3BA • µ PD70F3032AGF-3BA • µ PD703030AYGF-xxx-3BA • µ PD703032AYGF-xxx-3BA • µ PD70F3032AYGF-3BA • µ PD703031AGF-xxx-3BA • µ PD703033AGF-xxx-3BA • µ PD70F3033AGF-3BA • µ PD703031AYGF-xxx-3BA • µ PD703033AYGF-xxx-3BA •...
Page 36 CHAPTER 1 INTRODUCTION Pin names (V850/SB1) A1 to A21: Address bus P70 to P77: Port 7 AD0 to AD15: Address/data bus P80 to P83: Port 8 ADTRG: AD trigger input P90 to P96: Port 9 ANI0 to ANI11: Analog input P100 to P107: Port 10 ASCK0, ASCK1:...
Page 37: Function Blocks (V850/Sb1)
CHAPTER 1 INTRODUCTION 1.2.5 Function blocks (V850/SB1) (1) Internal block diagram HLDRQ (P96) INTC Instruction HLDAK (P95) INTP0 to INTP6 correction queue Note ASTB (P94) DSTB/RD (P93) TI00,TI01, 32-bit barrel Multiplier R/W /WRH (P92) TI10,TI11 Timer/counter shifter 16 ×16→32 UBEN (P91) TO0,TO1 16-bit timer: LBEN/WRL (P90)
Page 38 CHAPTER 1 INTRODUCTION (2) Internal units (a) CPU The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. Other dedicated on-chip hardware, such as the multiplier (16 bits × 16 bits → 32 bits) and the barrel shifter (32 bits) help accelerate processing of complex instructions.
Page 39 CHAPTER 1 INTRODUCTION (g) Timer/counter A two-channel 16-bit timer/event counter, a four-channel 8-bit timer/event counter, and a two-channel 8- bit interval timer are equipped, enabling measurement of pulse intervals and frequency as well as programmable pulse output. The two-channel 8-bit timer/event counter can be connected via a cascade to enable use as a 16-bit timer.
Page 40 CHAPTER 1 INTRODUCTION (n) Ports As shown below, the following ports have general-purpose port functions and control pin functions. Port Port Function Control Function Port 0 8-bit I/O General- NMI, external interrupt, A/D converter trigger, RTP trigger purpose port Port 1 6-bit I/O Serial interface Port 2...
Page 41: V850/Sb2
CHAPTER 1 INTRODUCTION 1.3 V850/SB2 1.3.1 Features (V850/SB2) Number of instructions: 74 Minimum instruction execution time 79 ns (operating at 12.58 MHz, external power supply 5 V, regulator output 3.0 V) 32 bits × 32 registers General-purpose registers Signed multiplication (16 × 16 → 32): 158 ns (operating at 12.58 MHz) Instruction set (able to execute instructions in parallel continuously without creating any register hazards).
Page 42: Application Fields (V850/Sb2)
CHAPTER 1 INTRODUCTION C bus interface (I (only for µ PD703034AY, 703035AY, 703036AY, 703037AY, 70F3035AY, and 70F3037AY) 8-/16-bit variable-length serial interface CSI/UART: 2 channels CSI/I 2 channels CSI (8-/16-bit valuable): 1 channel Dedicated baud rate generator: 3 channels A/D converter 10-bit resolution: 12 channels Internal RAM ←→...
Page 43: Ordering Information (V850/Sb2)
CHAPTER 1 INTRODUCTION 1.3.3 Ordering information (V850/SB2) Part Number Package Internal ROM µ PD703034AGC-xxx-8EU 100-pin plastic LQFP (fine pitch) (14 × 14) Mask ROM (128 KB) µ 100-pin plastic QFP (14 × 20) PD703034AGF-xxx-3BA Mask ROM (128 KB) µ 100-pin plastic LQFP (fine pitch) (14 × 14) PD703034AYGC-xxx-8EU Mask ROM (128 KB) µ...
Page 44: Pin Configuration (Top View) (V850/Sb2)
CHAPTER 1 INTRODUCTION 1.3.4 Pin configuration (top view) (V850/SB2) 100-pin plastic LQFP (fine pitch) (14 × 14) • µ PD703034AGC-xxx-8EU • µ PD70F3035AGC-8EU • µ PD703034AYGC-xxx-8EU • µ PD70F3035AYGC-8EU • µ PD703035AGC-xxx-8EU • µ PD703035AYGC-xxx-8EU P21/SO2 P71/ANI1 Note 2 P70/ANI0 P22/SCK2/SCL1 P23/RXD1/SI3 P24/TXD1/SO3...
Page 45 CHAPTER 1 INTRODUCTION 100-pin plastic QFP (14 × 20) • µ PD703034AGF-xxx-3BA • µ PD703036AGF-xxx-3BA • µ PD70F3035AGF-3BA • µ PD703034AYGF-xxx-3BA • µ PD703036AYGF-xxx-3BA • µ PD70F3035AYGF-3BA • µ PD703035AGF-xxx-3BA • µ PD703037AGF-xxx-3BA • µ PD70F3037AGF-3BA • µ PD703035AYGF-xxx-3BA • µ PD703037AYGF-xxx-3BA •...
Page 46 CHAPTER 1 INTRODUCTION Pin names (V850/SB2) A1 to A21: Address bus P70 to P77: Port 7 AD0 to AD15: Address/data bus P80 to P83: Port 8 ADTRG: AD trigger input P90 to P96: Port 9 ANI0 to ANI11: Analog input P100 to P107: Port 10 ASCK0, ASCK1:...
Page 47: Function Blocks (V850/Sb2)
CHAPTER 1 INTRODUCTION 1.3.5 Function blocks (V850/SB2) (1) Internal block diagram HLDRQ (P96) INTC Instruction HLDAK (P95) INTP0 to INTP6 correction queue Note ASTB (P94) DSTB/RD (P93) TI00,TI01, 32-bit barrel Multiplier R/W /WRH (P92) TI10,TI11 Timer/counter shifter 16 ×16→32 UBEN (P91) TO0,TO1 16-bit timer: LBEN/WRL (P90)
Page 48 CHAPTER 1 INTRODUCTION (2) Internal units (a) CPU The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. Other dedicated on-chip hardware, such as the multiplier (16 bits × 16 bits → 32 bits) and the barrel shifter (32 bits) help accelerate processing of complex instructions.
Page 49 CHAPTER 1 INTRODUCTION (g) Timer/counter A two-channel 16-bit timer/event counter, a four-channel 8-bit timer/event counter, and a two-channel 8- bit interval timer are equipped, enabling measurement of pulse intervals and frequency as well as programmable pulse output. The two-channel 8-bit timer/event counter can be connected via a cascade to enable use as a 16-bit timer.
Page 50 CHAPTER 1 INTRODUCTION (n) Ports As shown below, the following ports have general-purpose port functions and control pin functions. Port Port Function Control Function Port 0 8-bit I/O General- NMI, external interrupt, A/D converter trigger, RTP trigger purpose port Port 1 6-bit I/O Serial interface Port 2...
Page 51: Chapter 2 Pin Functions
CHAPTER 2 PIN FUNCTIONS 2.1 List of Pin Functions The names and functions of pins of the V850/SB1 and V850/SB2 are described below with dividing into port pins and non-port pins. There are three types of power supplies for the pin I/O buffers: AV , BV , and EV .
Page 52 CHAPTER 2 PIN FUNCTIONS (1) Port pins (1/3) Pin Name PULL Function Alternate Function Port 0 8-bit I/O port INTP0 Input/output mode can be specified in 1-bit units. INTP1 INTP2 INTP3 INTP4/ADTRG INTP5/RTPTRG INTP6 Port 1 SI0/SDA0 6-bit I/O port Input/output mode can be specified in 1-bit units.
Page 53 CHAPTER 2 PIN FUNCTIONS (2/3) Pin Name PULL Function Alternate Function Port 3 TI00 8-bit I/O port TI01 Input/output mode can be specified in 1-bit units. TI10/SI4 TI11/SO4 TO0/A13/SCK4 TO1/A14 TI4/TO4/A15 TI5/TO5 Port 4 8-bit I/O port Input/output mode can be specified in 1-bit units. Port 5 8-bit I/O port Input/output mode can be specified in 1-bit units.
Page 54 CHAPTER 2 PIN FUNCTIONS (3/3) Pin Name PULL Function Alternate Function Input Port 7 ANI0 8-bit input port ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 Input Port 8 ANI8 4-bit input port ANI9 ANI10 ANI11 Port 9 LBEN/WRL 7-bit I/O port UBEN Input/output mode can be specified in 1-bit units.
Page 55 CHAPTER 2 PIN FUNCTIONS (2) Non-port pins (1/3) Pin Name PULL Function Alternate Function Output Lower address bus used for external memory expansion P110/WAIT A2 to A4 P111 to P113 A5 to A8 P100/RTP0/KR0 to P103/RTP3/KR3 P104/RTP4/KR4/IERX P105/RTP5/KR5/IETX A11, A12 P106/RTP6/KR6 to P107/RTP7/KR7 P34/TO0/SCK4...
Page 56 CHAPTER 2 PIN FUNCTIONS (2/3) Pin Name PULL Function Alternate Function INTP6 Input External interrupt request input (digital noise elimination for remote control) KR0 to KR3 Key return input P100/A5/RTP0 to P103/A8/RTP3 P104/A9/RTP4/IERX P105/A10/RTP5/IETX KR6, KR7 P106/A11/RTP6 to P107/A12/RTP7 LBEN Output External data bus’s lower byte enable signal output P90/WRL...
Page 57 CHAPTER 2 PIN FUNCTIONS (3/3) Pin Name PULL Function Alternate Function Output Serial transmit data output (3-wire type) for CSI0 to CSI3 P14/TXD0 P24/TXD1 Serial transmit data output for variable-length CSI4 (3-wire type) P33/TI11 TI00 Input Shared as external capture trigger input and external count clock input for TM0 TI01 External capture trigger input for TM0...
Page 58: Pin States
CHAPTER 2 PIN FUNCTIONS 2.2 Pin States The operating states of various pins are described below with reference to their operation modes. Table 2-3. Pin Operating State in Operation Mode Reset STOP Mode IDLE Mode HALT Mode Bus Hold Idle State Operation Mode AD0 to AD15 Hi-Z...
Page 59: Description Of Pin Functions
CHAPTER 2 PIN FUNCTIONS 2.3 Description of Pin Functions (1) P00 to P07 (Port 0) ∙∙∙ 3-state I/O Port 0 is an 8-bit I/O port in which input and output can be set in 1-bit units for input or output. P00 to P07 can function as I/O port pins and can also function as NMI inputs, external interrupt request inputs, external triggers for the A/D converter, and external triggers for the real-time output port.
Page 60 CHAPTER 2 PIN FUNCTIONS (2) P10 to P15 (Port 1) ∙∙∙ 3-state I/O Port 1 is a 6-bit I/O port in which input and output can be specified in 1-bit units. P10 to P15 can function as I/O port pins and can also operate as input or output pins for the serial interface. Port/control mode can be selected for each bit.
Page 61 CHAPTER 2 PIN FUNCTIONS (3) P20 to P27 (Port 2) ∙∙∙ 3-state I/O Port 2 is an 8-bit I/O port in which input and output can be specified in 1-bit units. P20 to P27 can function as I/O port pins, input or output pins for the serial interface, and input or output for the timer/counter.
Page 62 CHAPTER 2 PIN FUNCTIONS (4) P30 to P37 (Port 3) ∙∙∙ 3-state I/O Port 3 is an 8-bit I/O port in which input and output can be specified in 1-bit units. P30 to P37 can function as I/O port pins, input or output pins for the timer/counter, an address bus (A13 to A15) when memory is expanded externally, and serial interface I/O.
Page 63 CHAPTER 2 PIN FUNCTIONS (b) Control mode (external expansion mode) P40 to P47 can be set as AD0 to AD7 according to the contents of the memory expansion register (MM). AD0 to AD7 (Address/Data 0 to 7) ∙∙∙ 3-state I/O These comprise the multiplexed address/data bus that is used for external access.
Page 64 CHAPTER 2 PIN FUNCTIONS A16 to A21 (Address 16 to 21) ∙∙∙ output These comprise an address bus that is used for external access. These pins operate as the higher 6-bit address output pins within a 22-bit address. The output changes in synchronization with the rising edge of the clock in the T1 state of the bus cycle.
Page 65 CHAPTER 2 PIN FUNCTIONS (ii) UBEN (Upper Byte Enable) ∙∙∙ output This is an upper byte enable signal output pin for an external 16-bit data bus. During byte access of even-numbered addresses, these pins are set as inactive (high level). The output changes in synchronization with the rising edge of the clock in the T1 state of the bus cycle.
Page 66 CHAPTER 2 PIN FUNCTIONS (ix) WRH (Write Strobe High Level Data) ∙∙∙ output This is a write strobe signal output pin for the higher data in an external 16-bit data bus. Output occurs during the write cycle, similar to DSTB. (x) RD (Read) ∙∙∙...
Page 67 CHAPTER 2 PIN FUNCTIONS (b) Control mode A1 to A4 (Address 1 to 4) ∙∙∙ output These comprise the address bus that is used for external access. These pins operate as the lower 4- bit address output pins within a 22-bit address. The output changes in synchronization with the rising edge of the clock in the T1 state of the bus cycle.
Page 68 CHAPTER 2 PIN FUNCTIONS (21) BV (Ground for Bus Interface) This is the ground pin for the bus interface. (22) EV (Power Supply for Port) This is the positive power supply pin for I/O ports and alternate-function pins (except for the alternate-function ports of the bus interface).
Page 69: I/O Circuit Types, I/O Buffer Power Supply And Connection Of Unused Pins
CHAPTER 2 PIN FUNCTIONS 2.4 I/O Circuit Types, I/O Buffer Power Supply and Connection of Unused Pins (1/2) Alternate Function I/O Circuit Type Recommended Connection Method Buffer Power Supply Input: Individually connect to EV or EV via a resistor Output: Leave open P01 to P04 INTP0 to INTP3 INTP4/ADTRG...
Page 70 CHAPTER 2 PIN FUNCTIONS (2/2) Alternate Function I/O Circuit Type Recommended Connection Method Buffer Power Supply LBEN/WRL Input: Individually connect to EV or EV via a resistor Output: Leave open UBEN R/W/WRH DSTB/RD ASTB HLDAK HLDRQ P100 to P103 RTP0/A5/KR0 to 10-A Input: Individually connect to EV...
Page 71: I/O Circuit Of Pins
CHAPTER 2 PIN FUNCTIONS 2.5 I/O Circuit of Pins (1/2) Type 2 Type 5-A Pullup P-ch enable Data P-ch IN/OUT Schmitt-triggered input with hysteresis characteristics Output N-ch disable Input enable Type 4 Type 8-A Data Pullup P-ch P-ch enable Data P-ch IN/OUT Output...
Page 72 CHAPTER 2 PIN FUNCTIONS (2/2) Type 10-A Type 26 Pullup Pullup P-ch P-ch enable enable Data Data P-ch P-ch IN/OUT IN/OUT Open drain Open drain N-ch N-ch Output disable Output disable Type 16 Feedback cut-off P-ch User’s Manual U13850EJ4V0UM...
Page 73: Chapter 3 Cpu Functions
CHAPTER 3 CPU FUNCTIONS The CPU of the V850/SB1 and V850/SB2 is based on RISC architecture and executes most instructions in one clock cycle by using a 5-stage pipeline. 3.1 Features • Minimum instruction execution time: V850/SB1: 50 ns (@ 20 MHz internal operation) V850/SB2: 79 ns (@ 12.58 MHz internal operation) •...
Page 74: Cpu Register Set
CHAPTER 3 CPU FUNCTIONS 3.2 CPU Register Set The CPU registers of the V850/SB1 and V850/SB2 can be classified into two categories: a general-purpose program register set and a dedicated system register set. All the registers are 32 bits wide. For details, refer to V850 Family User’s Manual Architecture.
Page 75: Program Register Set
CHAPTER 3 CPU FUNCTIONS 3.2.1 Program register set The program register set includes general-purpose registers and a program counter. (1) General-purpose registers Thirty-two general-purpose registers, r0 to r31, are available. Any of these registers can be used as a data variable or address variable.
Page 76: System Register Set
CHAPTER 3 CPU FUNCTIONS 3.2.2 System register set System registers control the status of the CPU and hold interrupt information. Table 3-2. System Register Numbers System Register Name Usage Operation EIPC Interrupt status saving registers These registers save the PC and PSW when an exception or interrupt occurs.
Page 77 CHAPTER 3 CPU FUNCTIONS (2) Program status word (PSW) Figure 3-4. Program Status Word (PSW) After reset: 00000020H Symbol Reserved field (fixed to 0). Indicates that NMI processing is in progress. This flag is set when NMI is accepted, and disables multiple interrupts.
Page 78: Operation Modes
CHAPTER 3 CPU FUNCTIONS 3.3 Operation Modes The V850/SB1 and V850/SB2 have the following operation modes. (1) Normal operation mode (single-chip mode) After the system has been released from the reset status, the pins related to the bus interface are set for port mode, execution branches to the reset entry address of the internal ROM, and instruction processing written in the internal ROM is started.
Page 79: Address Space
CHAPTER 3 CPU FUNCTIONS 3.4 Address Space 3.4.1 CPU address space The CPUs of the V850/SB1 and V850/SB2 are of 32-bit architecture and support up to 4 GB of linear address space (data space) during operand addressing (data access). When referencing instruction addresses, linear address space (program space) of up to 16 MB is supported.
Page 80: Image
CHAPTER 3 CPU FUNCTIONS 3.4.2 Image The core CPU supports 4 GB of “virtual” addressing space, or 256 memory blocks, each containing 16 MB memory locations. In actuality, the same 16 MB block is accessed regardless of the values of bits 31 to 24 of the CPU address.
Page 81: Wrap-Around Of Cpu Address Space
CHAPTER 3 CPU FUNCTIONS 3.4.3 Wrap-around of CPU address space (1) Program space Of the 32 bits of the PC (program counter), the higher 8 bits are fixed to 0, and only the lower 24 bits are valid. Even if a carry or borrow occurs from bit 23 to 24 as a result of branch address calculation, the higher 8 bits ignore the carry or borrow and remain 0.
Page 82: Memory Map
CHAPTER 3 CPU FUNCTIONS 3.4.4 Memory map The V850/SB1 and V850/SB2 reserve areas as shown below. Figure 3-9. Memory Map Single-chip mode Single-chip mode (external expansion mode) xxFFFFFFH Internal peripheral Internal peripheral 4 KB I/O area I/O area xxFFF000H xxFFEFFFH 28 KB Internal RAM area Internal RAM area...
Page 83: Area
CHAPTER 3 CPU FUNCTIONS 3.4.5 Area (1) Internal ROM/flash memory area An area of 1 MB maximum is reserved for the internal ROM/flash memory area. (a) V850/SB1 ( µ µ µ µ PD703031A, 703031AY), V850/SB2 ( µ µ µ µ PD703034A, 703034AY) 128 KB are available for the addresses xx000000H to xx01FFFFH.
Page 84 CHAPTER 3 CPU FUNCTIONS (c) V850/SB1 ( µ µ µ µ PD703030A, 703030AY), V850/SB2 ( µ µ µ µ PD703036A, 703036AY) 384 KB are available for the addresses xx000000H to xx05FFFFH. Addresses xx060000H to xx0FFFFFH are an access-prohibited area Figure 3-12. Internal ROM Area (384 KB) x x 0 F F F F F H Access-prohibited area...
Page 85 CHAPTER 3 CPU FUNCTIONS Interrupt/exception table The V850/SB1 and V850/SB2 increase the interrupt response speed by assigning handler addresses corresponding to interrupts/exceptions. The collection of these handler addresses is called an interrupt/exception table, which is located in the internal ROM area. When an interrupt/exception request is granted, execution jumps to the handler address, and the program written at that memory address is executed.
Page 86 CHAPTER 3 CPU FUNCTIONS (2) Internal RAM area An area of 28 KB maximum is reserved for the internal RAM area. (a) V850/SB1 ( µ µ µ µ PD703031A, 703031AY), V850/SB2 ( µ µ µ µ PD703034A, 703034AY) 12 KB are available for the addresses xxFFC000H to xxFFEFFFH. Addresses xxFF8000H to xxFFBFFFH are an access-prohibited area Figure 3-14.
Page 87 CHAPTER 3 CPU FUNCTIONS (c) V850/SB1 ( µ µ µ µ PD703030A, 703030AY), V850/SB2 ( µ µ µ µ PD703036A, 703036AY) 20 KB are available for the addresses xxFFA000H to xxFFEFFFH. Addresses xxFF8000H to xxFF9FFFH are an access-prohibited area Figure 3-16. Internal RAM Area (20 KB) x x F F E F F F H Internal RAM x x F F A 0 0 0 H...
Page 88 CHAPTER 3 CPU FUNCTIONS (3) Internal peripheral I/O area A 4 KB area of addresses FFF000H to FFFFFFH is reserved as an internal peripheral I/O area. The V850/SB1 and V850/SB2 are provided with a 1 KB area of addresses FFF000H to FFF3FFH as a physical internal peripheral I/O area, and its image can be seen on the rest of the area (FFF400H to FFFFFFH).
Page 89 CHAPTER 3 CPU FUNCTIONS (4) External memory The V850/SB1 and V850/SB2 can use an area of up to 16 MB (xx100000H to xxFF7FFFH) for external memory accesses (in single-chip mode: external expansion). 64 K, 256 K, 1 M, or 4 MB of physical external memory can be allocated when the external expansion mode is specified.
Page 90: External Expansion Mode
CHAPTER 3 CPU FUNCTIONS Figure 3-20. External Memory Area (When Expanded to 4 MB) xxFFFFFFH Internal peripheral I/O Internal RAM xxFF7FFFH Image xxC00000H Physical external memory xxBFFFFFH 3FFFFFH Image External memory xx800000H xx7FFFFFH 000000H Image xx400000H xx3FFFFFH Image xx100000H xx0FFFFFH Internal ROM xx000000H 3.4.6 External expansion mode...
Page 91 CHAPTER 3 CPU FUNCTIONS (1) Memory expansion mode register (MM) This register sets the mode of each pin of ports 4, 5, 6, and 9. In the external expansion mode, an external device can be connected to the external memory area of up to 4 MB. However, the external device cannot be connected to the internal RAM area, internal peripheral I/O area, and internal ROM area in the single-chip mode (and even if the external device is connected physically, it cannot be accessed).
Page 92 CHAPTER 3 CPU FUNCTIONS (2) Memory address output mode register (MAM) Sets the mode of ports 3, 10, and 11. Separate output can be set for the address bus (A1 to A15) in the external expansion mode. The MAM register can be written in 8-bit units. If read is performed, undefined values will be read. However, bits 3 to 7 are fixed to 0.
Page 93: Recommended Use Of Address Space
CHAPTER 3 CPU FUNCTIONS 3.4.7 Recommended use of address space The architectures of the V850/SB1 and V850/SB2 require that a register that serves as a pointer be secured for address generation in operand data accessing for data space. The address in this pointer register ±32 KB can be accessed directly from instruction.
Page 94 CHAPTER 3 CPU FUNCTIONS Figure 3-24. Recommended Memory Map (Flash Memory Version) Program space Data space FFFFFFFFH Internal peripheral I/O FFFFF400H FFFFF3FFH FFFFF000H FFFFEFFFH Internal xxFFFFFFH Internal peripheral I/O FFFF8000H xxFFF400H FFFF7FFFH xxFFF3FFH External xxFFF000H memory xxFFEFFFH FF800000H FF7FFFFFH Internal xxFFB000H 01000000H xxFFAFFFH...
Page 95: Peripheral I/O Registers
CHAPTER 3 CPU FUNCTIONS 3.4.8 Peripheral I/O registers The differences in the peripheral I/O registers of the V850/SB1 and V850/SB2 are shown below. Table 3-4. Differences in Peripheral I/O Registers of V850/SB1 and V850/SB2 Peripheral I/O Register V850/SB1 V850/SB2 µ PD703030A, µ...
Page 96 CHAPTER 3 CPU FUNCTIONS (1/7) Address Function Register Name Symbol Bit Units for Manipulation After Reset 1 Bit 8 Bits 16 Bits 32 Bits Note FFFFF000H Port 0 √ √ FFFFF002H Port 1 √ √ FFFFF004H Port 2 √ √ FFFFF006H Port 3 √...
Page 97 CHAPTER 3 CPU FUNCTIONS (2/7) Address Function Register Name Symbol Bit Units for Manipulation After Reset 1 Bit 8 Bits 16 Bits 32 Bits FFFFF096H Pull-up resistor option register 11 PU11 √ √ FFFFF0A2H Port 1 function register √ √ FFFFF0A4H Port 2 function register √...
Page 98 CHAPTER 3 CPU FUNCTIONS (3/7) Address Function Register Name Symbol Bit Units for Manipulation After Reset 1 Bit 8 Bits 16 Bits 32 Bits FFFFF140H Interrupt control register CSIC4 √ √ FFFFF142H Interrupt control register IEBIC1 √ √ FFFFF144H Interrupt control register IEBIC2 √...
Page 99 CHAPTER 3 CPU FUNCTIONS (4/7) Address Function Register Name Symbol Bit Units for Manipulation After Reset 1 Bit 8 Bits 16 Bits 32 Bits FFFFF1D4H DMA byte count register 5 DBC5 Undefined √ FFFFF1D6H DMA channel control register 5 DCHC5 √...
Page 100 CHAPTER 3 CPU FUNCTIONS (5/7) Address Function Register Name Symbol Bit Units for Manipulation After Reset 1 Bit 8 Bits 16 Bits 32 Bits FFFFF26AH 16-bit counter 45 (during cascade connection TM45 0000H √ only) FFFFF26CH 16-bit compare register 45 (during cascade CR45 √...
Page 101 CHAPTER 3 CPU FUNCTIONS (6/7) Address Function Register Name Symbol Bit Units for Manipulation After Reset 1 Bit 8 Bits 16 Bits 32 Bits FFFFF2E2H Variable-length serial control register 4 CSIM4 √ √ FFFFF2E4H Variable-length serial setting register 4 CSIB4 √...
Page 102 CHAPTER 3 CPU FUNCTIONS (7/7) Address Function Register Name Symbol Bit Units for Manipulation After Reset 1 Bit 8 Bits 16 Bits 32 Bits FFFFF36CH Correction control register CORCN √ √ FFFFF36EH Correction request register CORRQ √ √ FFFFF370H Correction address register 0 CORAD0 00000000H √...
Page 103: Specific Registers
CHAPTER 3 CPU FUNCTIONS 3.4.9 Specific registers Specific registers are registers that are protected from being written with illegal data due to erroneous program execution, etc. The write access of these specific registers is executed in a specific sequence, and if abnormal store operations occur, it is notified by the system status register (SYS).
Page 104 CHAPTER 3 CPU FUNCTIONS A description example is given below. [Description example]: In case of PSC register LDSR rX,5 ; NP bit = 1 ST.B r0,PRCMD [r0] ; Write to PRCMD ST.B rD,PSC [r0] ; PSC register setting LDSR rY,5 ;...
Page 105 CHAPTER 3 CPU FUNCTIONS (1) Command register (PRCMD) The command register (PRCMD) is a register used when write-accessing the specific register to prevent incorrect writing to the specific registers due to the erroneous program execution. This register can be written in 8-bit units. It becomes undefined values in a read cycle. Occurrence of illegal store operations can be checked by the PRERR bit of the SYS register.
Page 106: Chapter 4 Bus Control Function
CHAPTER 4 BUS CONTROL FUNCTION The V850/SB1 and V850/SB2 are provided with an external bus interface function by which external memories such as ROM and RAM, and I/O can be connected. 4.1 Features • Address bus (capable of separate output) •...
Page 107 CHAPTER 4 BUS CONTROL FUNCTION 4.2.2 Control register (1) System control register (SYC) This register switches control signals for bus interface. The system control register can be read/written in 8-bit or 1-bit units. Figure 4-1. System Control Register (SYC) After reset: 00H Address: FFFFF064H Symbol <0>...
Page 108 CHAPTER 4 BUS CONTROL FUNCTION 4.3.2 Bus width CPU carries out peripheral I/O access and external memory access in 8-bit, 16-bit, or 32-bit. The following shows the operation for each access. (1) Byte access (8 bits) Byte access is divided into two types, the access to even address and the access to odd address. Figure 4-2.
Page 109 CHAPTER 4 BUS CONTROL FUNCTION 4.4 Memory Block Function The 16 MB memory space is divided into memory blocks of 1 MB units. The programmable wait function and bus cycle operation mode can be independently controlled for every two memory blocks. Figure 4-5.
Page 110 CHAPTER 4 BUS CONTROL FUNCTION 4.5 Wait Function 4.5.1 Programmable wait function To facilitate interfacing with low-speed memories and I/O devices, up to 3 data wait states can be inserted in a bus cycle that starts every two memory blocks. The number of wait states can be programmed by using data wait control register (DWC).
Page 111 CHAPTER 4 BUS CONTROL FUNCTION 4.5.2 External wait function When an extremely slow device, I/O, or asynchronous system is connected, any number of wait states can be inserted in a bus cycle by sampling the external wait pin (WAIT) to synchronize with the external device. The external wait signal is data wait only, and does not affect the access times of the internal ROM, internal RAM, and on-chip peripheral I/O areas, similar to programmable wait.
Page 112 CHAPTER 4 BUS CONTROL FUNCTION 4.6 Idle State Insertion Function To facilitate interfacing with low-speed memory devices and meeting the data output float delay time on memory read accesses every two blocks, one idle state (TI) can be inserted into the current bus cycle after the T3 state. The bus cycle following continuous bus cycles starts after one idle state.
Page 113 CHAPTER 4 BUS CONTROL FUNCTION 4.7 Bus Hold Function 4.7.1 Outline of function When the MM3 bit of the memory expansion mode register (MM) is set (1), the HLDRQ and HLDAK pin functions of P95 and P96 become valid. When the HLDRQ pin becomes active (low) indicating that another bus master is requesting acquisition of the Note bus, the external address/data bus and strobe pins go into a high-impedance state , and the bus is released (bus...
Page 114 CHAPTER 4 BUS CONTROL FUNCTION 4.7.2 Bus hold procedure The procedure of the bus hold function is illustrated below. Figure 4-10. Bus Hold Procedure <1>HLDRQ = 0 accepted Nomal status <2>All bus cycle start request pending <3>End of current bus cycle <4>Bus idle status <5>HLDAK = 0 Bus hold status...
Page 115 CHAPTER 4 BUS CONTROL FUNCTION 4.8 Bus Timing The V850/SB1 and V850/SB2 can execute the read/write control for an external device by the following two modes. • Mode using DSTB, R/W, LBEN, UBEN, and ASTB signals • Mode using RD, WRL, WRH, and ASTB signals Set these modes by using the BIC bit of the system control register (SYC) (see Figure 4-1).
Page 116 CHAPTER 4 BUS CONTROL FUNCTION Figure 4-11. Memory Read (2/4) (b) 1 wait CLKOUT (output) Address A16 to A21 (output) Address A1 to A15 (output) AD0 to AD15 Address Data (input/output) ASTB (output) R/W (output) WRH, WRL (output) DSTB, RD (output) UBEN, LBEN (output) WAIT (input) Remarks 1.
Page 117 CHAPTER 4 BUS CONTROL FUNCTION Figure 4-11. Memory Read (3/4) (c) 0 wait, idle state CLKOUT (output) Address A16 to A21 (output) Address A1 to A15 (output) AD0 to AD15 Address Data (input/output) ASTB (output) R/W (output) WRH, WRL (output) DSTB, RD (output) UBEN, LBEN (output) WAIT (input)
Page 118 CHAPTER 4 BUS CONTROL FUNCTION Figure 4-11. Memory Read (4/4) (d) 1 wait, idle state CLKOUT (output) Address A16 to A21 (output) Address A1 to A15 (output) AD0 to AD15 Address Data (input/output) ASTB (output) R/W (output) WRH, WRL (output) DSTB, RD (output) UBEN, LBEN (output) WAIT (input)
Page 119 CHAPTER 4 BUS CONTROL FUNCTION Figure 4-12. Memory Write (1/2) (a) 0 wait CLKOUT (output) A16 to A21 (output) Address Address A1 to A15 (output) AD0 to AD15 Note Address Data (input/output) ASTB (output) R/W (output) RD (output) DSTB (output) WRH, WRL (output) UBEN, LBEN (output) WAIT (input)
Page 120 CHAPTER 4 BUS CONTROL FUNCTION Figure 4-12. Memory Write (2/2) (b) 1 wait CLKOUT (output) A16 to A21 (output) Address A1 to A15 (output) Address AD0 to AD15 Note Address Data (input/output) ASTB (output) R/W (output) RD (output) DSTB (output) WRH, WRL (output) UBEN, LBEN (output) WAIT (input)
Page 121 CHAPTER 4 BUS CONTROL FUNCTION Figure 4-13. Bus Hold Timing CLKOUT (output) HLDRQ (input) Note 1 HLDAK (output) A16 to A21 (output) Address Address A1 to A15 (output) Address AD0 to AD15 Undefined Address Data Address (input/output) ASTB (output) Note 2 R/W (output) DSTB, RD, WRH, WRL (output)
Page 122 CHAPTER 4 BUS CONTROL FUNCTION 4.9 Bus Priority There are four external bus cycles: bus hold, operand data access, instruction fetch (branch), and instruction fetch (continuous). The bus hold cycle is given the highest priority, followed by operand data access, instruction fetch (branch), and instruction fetch (continuous) in that order.
Page 123 CHAPTER 4 BUS CONTROL FUNCTION 4.10 Memory Boundary Operation Condition 4.10.1 Program space (1) Do not execute branch to the on-chip peripheral I/O area or continuous fetch from the internal RAM area to peripheral I/O area. If branch or instruction fetch is executed nevertheless, the NOP instruction code is continuously fetched and not fetched from external memory.
Page 124 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.1 Outline The V850/SB1 and V850/SB2 are provided with a dedicated interrupt controller (INTC) for interrupt servicing and realize a high-powered interrupt function that can service interrupt requests from a total of 37 to 40 sources. An interrupt is an event that occurs independently of program execution, and an exception is an event that occurs dependent on program execution.
Page 125 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 5-1. Interrupt Source List (1/2) Type Classifi- Default Name Trigger Inter- Exception Handler Restored Interrupt cation Priority rupt Code Address Control Source Register − − − Reset Interrupt RESET Reset input 0000H 00000000H Unde- fined −...
Page 126 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 5-1. Interrupt Source List (2/2) Type Classifi- Default Name Trigger Interrupt Exception Handler Restored Interrupt cation Priority Source Code Address Control Register Maskable Interrupt INTCSI2 CSI2 transmit end CSI2 0230H 00000230H nextPC CSIC2 Note 1 INTIIC1 C1 interrupt 0240H...
Page 127 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.2 Non-Maskable Interrupt A non-maskable interrupt is acknowledged unconditionally, even when interrupts are disabled (DI state). An NMI is not subject to priority control and takes precedence over all other interrupts. The following two non-maskable interrupt requests are available in the V850/SB2. •...
Page 128 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.2.1 Operation If the non-maskable interrupt is generated, the CPU performs the following processing, and transfers control to the handler routine: (1) Saves the restored PC to FEPC. (2) Saves the current PSW to FEPSW. (3) Writes exception code 0010H to the higher half-word (FECC) of ECR.
Page 129 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 5-2. Acknowledging Non-Maskable Interrupt Request (a) If a new NMI request is generated while an NMI service routine is executing: Main routine (PSW. NP = 1) NMI request NMI request NMI request pending because PSW. NP = 1 Pending NMI request processed (b) If a new NMI request is generated twice while an NMI service routine is executing: Main routine...
Page 130 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.2.2 Restore Execution is restored from non-maskable interrupt servicing by the RETI instruction. Operation of RETI instruction When the RETI instruction is executed, the CPU performs the following processing, and transfers control to the address of the restored PC. (1) Restores the values of PC and PSW from FEPC and FEPSW, respectively, because the EP bit of PSW is 0 and the NP bit of PSW is 1.
Page 131 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.2.3 NP flag The NP flag is a status flag that indicates that non-maskable interrupt (NMI) servicing is under execution. This flag is set when the NMI interrupt request has been acknowledged, and masks all interrupt requests to prohibit multiple interrupts from being acknowledged.
Page 132 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.2.5 Edge detection function of NMI pin The NMI pin valid edge can be selected from the following four types: falling edge, rising edge, both edges, detects neither rising nor falling edge. Rising edge specification register 0 (EGP0) and falling edge specification register 0 (EGN0) specify the valid edge of the non-maskable interrupt (NMI).
Page 133 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.3 Maskable Interrupts Maskable interrupt requests can be masked by interrupt control registers. The V850/SB1 and V850/SB2 have 37 to 40 maskable interrupt sources (see 5.1.1 Features). If two or more maskable interrupt requests are generated at the same time, they are acknowledged according to the default priority.
Page 134 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 5-7. Maskable Interrupt Servicing INT input INTC accepted Mask? PSW. ID = 0 Interrupt enable mode? Priority higher than that of interrupt currently serviced? Priority higher than that of other interrupt request? Highest default priority of interrupt requests with the same priority? Maskable interrupt request...
Page 135 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.3.2 Restore To restore execution from the maskable interrupt servicing, the RETI instruction is used. Operation of RETI instruction When the RETI instruction is executed, the CPU performs the following steps, and transfers control to the address of the restored PC.
Page 136 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.3.3 Priorities of maskable interrupts The V850/SB1 and V850/SB2 provide a multiple interrupt service in which an interrupt is acknowledged while another interrupt is being serviced. Multiple interrupts can be controlled by priority levels. There are two types of priority level control: control based on the default priority levels, and control based on the programmable priority levels which are specified by interrupt priority level specification bit (xxPRn).
Page 137 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 5-9. Example of Interrupt Nesting Service (1/2) Main routine Servicing of a Servicing of b Interrupt Interrupt request a request b Interrupt request b is acknowledged because the priority of (level 3) (level 2) b is higher than that of a and interrupts are enabled.
Page 138 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 5-9. Example of Interrupt Nesting Process (2/2) Main routine Servicing of i Processing of k Interrupt request j Interrupt request i (level 3) (level 2) Interrupt request j is held pending because its Interrupt request k priority is lower than that of i.
Page 139 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 5-10. Example of Servicing Interrupt Requests Generated Simultaneously Main routine Interrupt request a (level 2) Note 1 Interrupt request b (level 1) Interrupt request b and c are Servicing of interrupt request b • Note 2 Interrupt request c (level 1) acknowledged first according to their...
Page 140 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 5-11. Interrupt Control Register (xxICn) Format After reset: 47H Address: FFFFF100H to FFFFF156H Symbol <7> <6> xxICn xxIFn xxMKn xxPRn2 xxPRn1 xxPRn0 Note Interrupt request flag xxIFn Interrupt request not generated Interrupt request generated xxMKn Interrupt mask flag Enables interrupt servicing...
Page 141 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION Address and bit of each interrupt control register is as follows: Table 5-2. Interrupt Control Register (xxICn) Address Register <7> <6> FFFFF100H WDTIC WDTIF WDTMK WDTPR2 WDTPR1 WDTPR0 FFFFF102H PIC0 PIF0 PMK0 PPR02 PPR01 PPR00 FFFFF104H PIC1 PIF1...
Page 142 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.3.5 In-service priority register (ISPR) This register holds the priority level of the maskable interrupt currently acknowledged. When an interrupt request is acknowledged, the bit of this register corresponding to the priority level of that interrupt is set to 1 and remains set while the interrupt is serviced.
Page 143 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.3.7 Watchdog timer mode register (WDTM) Read/write is available in 8- or 1-bit units (for details, refer to CHAPTER 9 WATCHDOG TIMER). Figure 5-14. Watchdog Timer Mode Register (WDTM) Format After reset: 00H Address: FFFFF384H Symbol <7>...
Page 144 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION (3) Noise elimination of INTP6 pin The INTP6 pin incorporates a digital noise eliminator. The sampling clock for digital sampling can be selected from among f /64, f /128, f /256, f /512, f /1024, and f .
Page 145 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.3.9 Edge detection function Valid edges of the INTP0 to INTP6 pins can be selected for each pin from the following four types. • Rising edge • Falling edge • Both rising and falling edges •...
Page 146 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.4 Software Exception A software exception is generated when the CPU executes the TRAP instruction, and can be always accepted. • TRAP instruction format: TRAP vector (where vector is 0 to 1FH) For details of the instruction function, refer to the V850 Family User’s Manual Architecture. 5.4.1 Operation If a software exception occurs, the CPU performs the following processing, and transfers control to the handler routine:...
Page 147 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.4.2 Restore To restore or return execution from the software exception service routine, the RETI instruction is used. Operation of RETI instruction When the RETI instruction is executed, the CPU performs the following steps, and transfers control to the address of the restored PC.
Page 148 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.4.3 EP flag The EP flag in PSW is a status flag used to indicate that exception processing is in progress. It is set when on exception occurs, and the interrupt is disabled. Figure 5-18. EP Flag (EP) After reset: 00000020H Symbol NP EP ID SAT CY OV...
Page 149 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION How the exception trap is processed is shown below. Figure 5-20. Exception Trap Processing Exception trap (ILGOP) occurs CPU processing EIPC Restored PC EIPSW ECR.EICC Exception code PSW.EP PSW.ID 00000060H Exception processing User’s Manual U13850EJ4V0UM...
Page 150 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.5.3 Restore To restore or return execution from the exception trap, the RETI instruction is used. Operation of RETI instruction When the RETI instruction is executed, the CPU performs the following processing, and transfers control to the address of the restored PC.
Page 151 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.6 Priority Control 5.6.1 Priorities of interrupts and exceptions Table 5-3. Priorities of Interrupts and Exceptions RESET TRAP ILGOP RESET × ← ← ← × ↑ ← ← × ↑ ↑ ← TRAP ILGOP × ↑...
Page 152 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION (1) To acknowledge maskable interrupts in service program Service program of maskable interrupt or exception • Saves EIPC to memory or register • Saves EIPSW to memory or register • EI instruction (enables interrupt acknowledgement) ←...
Page 153 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION Priorities 0 to 7 (0 is the highest) can be programmed for each maskable interrupt request for multiple interrupt processing control. To set a priority level, write values to the xxPRn0 to xxPRn2 bits of the interrupt request control register (xxICn) corresponding to each maskable interrupt request.
Page 154 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.7 Interrupt Latency Time The following table describes the interrupt latency time (from interrupt request generation to start of interrupt servicing). Figure 5-22. Pipeline Operation at Interrupt Request Acknowledgement 7 to 14 system clocks 4 system clocks System clock Interrupt request Instruction 1...
Page 155 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION Even when the EI instruction is executed, a period of time is required to identify an interrupt. Consequently, at least seven clocks are required until an interrupt request is acknowledged after the EI instruction has been executed.
Page 156 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.9 Key Interrupt Function Key interrupt can be generated by inputting a falling edge to key input pins (KR0 to KR7) by means of setting the key return mode register (KRM). The key return mode register (KRM) includes 5 bits. The KRM0 bit controls the KR0 to KR3 signals in 4-bit units and the KRM4 to KRM7 bits control corresponding signals from KR4 to KR7 (arbitrary setting from 4 to 8 bits is possible).
Page 157 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 5-24. Key Return Block Diagram INTKR KRM7 KRM6 KRM5 KRM4 KRM0 Key return mode register (KRM) User’s Manual U13850EJ4V0UM...
Page 158 CHAPTER 6 CLOCK GENERATION FUNCTION 6.1 Outline The clock generator is a circuit that generates the clock pulses that are supplied to the CPU and peripheral hardware. There are two types of system clock oscillators. (1) Main system clock oscillator The oscillator of V850/SB1 has an oscillation frequency of 2 to 20 MHz.
Page 159 CHAPTER 6 CLOCK GENERATION FUNCTION 6.2 Composition Figure 6-1. Clock Generator Subsystem Clock supplied to clock watch timer, etc. oscillator IDLE IDLE control Main system IDLE Prescaler HALT clock control oscillator CPU clock HALT Selector STOP, control Clock supplied to Prescaler peripheral hardware CLKOUT...
Page 160 CHAPTER 6 CLOCK GENERATION FUNCTION 6.3 Clock Output Function This function outputs the CPU clock via the CLKOUT pin. When clock output is enabled, the CPU clock is output via the CLKOUT pin. When it is disabled, a low-level signal is output via the CLKOUT pin. Output is stopped in the IDLE or STOP mode (fixed to low level).
Page 161 CHAPTER 6 CLOCK GENERATION FUNCTION Cautions 1. While CLKOUT is output, do not change the CPU clock (the value of the CK2 to CK0 in the PCC register). 2. Even if the MCK bit is set to 1 during main clock operation, the main clock is not stopped. The CPU clock stops after the sub clock is selected.
Page 162 CHAPTER 6 CLOCK GENERATION FUNCTION (2) Power save control register (PSC) This is a specific register. It can be written to only when a specified combination of sequences is used. For details, see 3.4.9 Specific registers. This register can be read/written in 8- or 1-bit units. Figure 6-3.
Page 163 CHAPTER 6 CLOCK GENERATION FUNCTION (3) Oscillation stabilization time selection register (OSTS) This register can be read/written in 8-bit units. Figure 6-4. Format of Oscillation Stabilization Time Selection Register (OSTS) After reset: Address: FFFFF380H OSTS OSTS2 OSTS1 OSTS0 OSTS2 OSTS1 OSTS0 Selection of oscillation stabilization time Clock...
Page 164 CHAPTER 6 CLOCK GENERATION FUNCTION 6.4 Power Save Functions 6.4.1 Outline This product provides the following power saving functions. These modes can be combined and switched to suit the target application, which enables effective implementation of low-power systems. (1) HALT mode When in this mode, the clock’s oscillator continues to operate but the CPU’s operating clock is stopped.
Page 165 CHAPTER 6 CLOCK GENERATION FUNCTION 6.4.2 HALT mode (1) Settings and operating states When in this mode, the clock’s oscillator continues to operate but the CPU’s operating clock is stopped. A clock continues to be supplied for other on-chip peripheral functions to maintain operation of those functions. When HALT mode is set while the CPU is idle, it enables the system’s total power consumption to be reduced.
Page 166 CHAPTER 6 CLOCK GENERATION FUNCTION Table 6-1. Operating Statuses in HALT Mode (1/2) HALT Mode Setting When CPU Operates with Main Clock When CPU Operates with Sub Clock When Subclock Exists When Subclock Does When Main Clock’s When Main Clock’s Item Not Exist Oscillation Continues...
Page 167 CHAPTER 6 CLOCK GENERATION FUNCTION Table 6-1. Operating Statuses in HALT Mode (2/2) HALT Mode Setting When CPU Operates with Main Clock When CPU Operates with Sub Clock When Subclock Does When Subclock Exists When Main Clock’s When Main Clock’s Item Not Exist Oscillation Continues...
Page 168 CHAPTER 6 CLOCK GENERATION FUNCTION 6.4.3 IDLE mode (1) Settings and operating states This mode stops the entire system except the watch timer by stopping the on-chip main clock supply while the clock oscillator is still operating. Supply to the sub clock continues. When this mode is canceled, there is no need for the oscillator to wait for the oscillation stabilization time, so normal operation can be resumed quickly.
Page 169 CHAPTER 6 CLOCK GENERATION FUNCTION Table 6-2. Operating Statuses in IDLE Mode (2/2) IDLE Mode Settings When Sub Clock Exists When Sub Clock Does Not Exist Item External bus interface Stopped External Operating interrupt INTP0 to INTP3 Operating request INTP4 and INTP5 Stopped INTP6 Operates when f is selected for sampling...
Page 170 CHAPTER 6 CLOCK GENERATION FUNCTION 6.4.4 Software STOP mode (1) Settings and operating states This mode stops the entire system by stopping the main clock oscillator to stop supplying the internal main clock. The sub clock oscillator continues operating and the on-chip sub clock supply is continued. When the FRC bit in the processor clock control register (PCC) is set to 1, the sub clock oscillator’s on-chip feedback resistor is cut.
Page 171 CHAPTER 6 CLOCK GENERATION FUNCTION Table 6-3. Operating Statuses in Software STOP Mode (2/2) Mode Settings When Sub Clock Exists When Sub Clock Does Not Exist Item DMA0 to DMA5 Stopped Real-time output Operates when INTTM4 or INTTM5 has been Stopped selected (when TM4 or TM5 is operating) Port function...
Page 172 CHAPTER 6 CLOCK GENERATION FUNCTION 6.5 Oscillation Stabilization Time The following shows methods for specifying the length of oscillation stabilization time required to stabilize the oscillator following cancellation of STOP mode. (1) Cancellation by non-maskable interrupt or by unmasked interrupt request STOP mode is canceled by a non-maskable interrupt or an unmasked interrupt request.
Page 173 CHAPTER 6 CLOCK GENERATION FUNCTION 6.6 Notes on Power Save Function If the V850/SB1 or V850/SB2 is used under the following conditions, the address indicated by the program counter (PC) differs from the address that actually reads an instruction after the power save mode has been released. Of the instructions 4 to 16 bytes after the instruction that writes data to the PSC register, the CPU may ignore 4 or 8 bytes of the instruction and execute wrong instructions.
Page 174 CHAPTER 7 TIMER/COUNTER FUNCTION 7.1 16-Bit Timer (TM0, TM1) 7.1.1 Outline • 16-bit capture/compare registers: 2 (CRn0, CRn1) • Independent capture/trigger inputs: 2 (TIn0, TIn1) • Support of output of capture/match interrupt request signals (INTTMn0, INTTMn1) • Event input (shared with TIn0) via digital noise eliminator and support of edge specifications •...
Page 175 CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-1. Block Diagram of TM0 and TM1 Internal bus Capture/compare control register n (CRCn) CRCn2 CRCn1 CRCn0 Selector INTTMn0 16-bit capture/compare Noise Selector TIn1 register n0 (CRn0) eliminator Match Count clock Note Clear 16-bit timer register (TMn) Selector Output controller...
Page 176 CHAPTER 7 TIMER/COUNTER FUNCTION (5) Square wave output Can output a square wave of any frequency. (6) One-shot pulse output Can output a one-shot pulse with any output pulse width. 7.1.3 Configuration Timers 0 and 1 include the following hardware. Table 7-1.
Page 177 CHAPTER 7 TIMER/COUNTER FUNCTION (2) Capture/compare registers n0 (CR00, CR10) CRn0 is a 16-bit register that functions as a capture register and as a compare register. Whether this register functions as a capture or compare register is specified by using bit 0 (CRCn0) of the CRCn register. (a) When using CRn0 as compare register The value set to CRn0 is always compared with the count value of the TMn register.
Page 178 CHAPTER 7 TIMER/COUNTER FUNCTION (3) Capture/compare register n1 (CR01, CR11) This is a 16-bit register that can be used as a capture register and a compare register. Whether it is used as a capture register or compare register is specified by bit 2 (CRCn2) of the CRCn register. (a) When using CRn1 as compare register The value set to CRn1 is always compared with the count value of TMn.
Page 179 CHAPTER 7 TIMER/COUNTER FUNCTION 7.1.4 Timer 0, 1 control registers The registers to control timers 0, 1 are shown below. • 16-bit timer mode control register n (TMCn) • Capture/compare control register n (CRCn) • 16-bit timer output control register n (TOCn) •...
Page 180 CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-2. 16-Bit Timer Mode Control Registers 0, 1 (TMC0, TMC1) After reset: 00H Address: FFFFF208H, FFFFF218H <0> TMCn TMCn3 TMCn2 TMCn1 OVFn (n = 0, 1) TMCn3 TMCn2 TMCn1 Selects operation mode Selects TOn output Generation of interrupt and clear mode timing...
Page 181 CHAPTER 7 TIMER/COUNTER FUNCTION Cautions 1. When the bit other than the OVFn flag is written, be sure to stop the timer operation. 2. The valid edge of the TIn0 pin is set by using prescaler mode register n0 (PRMn0). 3.
Page 182 CHAPTER 7 TIMER/COUNTER FUNCTION (3) 16-bit timer output control registers 0, 1 (TOC0, TOC1) TOCn controls the operation of the timer n output controller by setting or resetting the R-S flip-flop (LV0), enabling or disabling reverse output, enabling or disabling output of timer n, enabling or disabling one-shot pulse output operation, and selecting an output trigger for a one-shot pulse by software.
Page 183 CHAPTER 7 TIMER/COUNTER FUNCTION Cautions 1. Before setting TOCn, be sure to stop the timer operation. 2. LVSn and LVRn are 0 when read after data have been set to them. 3. OSPTn is 0 when read because it is automatically cleared after data has been set. 4.
Page 184 CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-6. Prescaler Mode Register 01 (PRM01) After reset: 00H R/W Address: FFFFF20EH Note PRM01 PRM02 Note Set together with bits 0 and 1 of the PRM00 register. (See Figure 7-5) Cautions 1. When selecting the valid edge of TI0n as the count clock, do not specify the valid edge of TI0n to clear and start the timer and as a capture trigger.
Page 185 CHAPTER 7 TIMER/COUNTER FUNCTION (5) Prescaler mode registers 10, 11 (PRM10, PRM11) PRM1n selects a count clock of the 16-bit timer (TM1) and the valid edge of TI1n input. PRM10 and PRM11 are set by an 8-bit memory manipulation instruction. RESET input clears PRM10 and PRM11 to 00H.
Page 186 CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-8. Prescaler Mode Register 11 (PRM11) After reset: 00H R/W Address: FFFFF21EH Note PRM11 PRM12 Note Set together with bits 0 and 1 of the PRM10 register. (See Figure 7-7) Cautions 1. When selecting the valid edge of TI1n as the count clock, do not specify the valid edge of TI1n to clear and start the timer and as a capture trigger.
Page 187 CHAPTER 7 TIMER/COUNTER FUNCTION 7.2 16-Bit Timer Operation 7.2.1 Operation as interval timer (16 bits) TMn operates as an interval timer when 16-bit timer mode control register n (TMCn) and capture/compare control register n (CRCn) are set as shown in Figure 7-9 (n = 0, 1). In this case, TMn repeatedly generates an interrupt at the time interval specified by the count value set in advance to 16-bit capture/compare register n (CRn0).
Page 188 CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-10. Configuration of Interval Timer 16-bit capture/compare register n0 (CRn0) INTTMn0 Note Count clock Selector 16-bit timer register n (TMn) OVFn Noise TIn0 eliminator Clear circuit Note The count clock is set by the PRMn0 and PRMn1 registers. Remarks 1.
Page 189 CHAPTER 7 TIMER/COUNTER FUNCTION 7.2.2 PPG output operation TMn can be used for PPG (Programmable Pulse Generator) output by setting 16-bit timer mode control register n (TMCn) and capture/compare control register n (CRCn) as shown in Figure 7-12. The PPG output function outputs a square wave from the TOn pin with a cycle specified by the count value set in advance to 16-bit capture/compare register n0 (CRn0) and a pulse width specified by the count value set in advance to 16-bit capture/compare register n1 (CRn1).
Page 190 CHAPTER 7 TIMER/COUNTER FUNCTION 7.2.3 Pulse width measurement 16-bit timer register n (TMn) can be used to measure the pulse widths of the signals input to the TIn0 and TIn1 pins. Measurement can be carried out with TMn used as a free-running counter or by restarting the timer in synchronization with the edge of the signal input to the TIn0 pin.
Page 191 CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-14. Configuration for Pulse Width Measurement with Free-Running Counter Note Count clock OVFn Selector 16-bit timer register n (TMn) 16-bit capture/compare register n1 TIn0 (CRn1) INTTMn1 Internal bus Note The count clock is set by the PRMn0 and PRMn1 registers. Remarks 1.
Page 192 CHAPTER 7 TIMER/COUNTER FUNCTION (2) Measurement of two pulse widths with free-running counter The pulse widths of the two signals respectively input to the TIn0 and TIn1 pins can be measured when 16-bit timer register n (TMn) is used as a free-running counter (refer to Figure 7-16). When the edge specified by bits 4 and 5 (ESn00 and ESn01) of prescaler mode register n0 (PRMn0) is input to the TIn0 pin, the value of the TMn is loaded to 16-bit capture/compare register n1 (CRn1) and an external interrupt request signal (INTTMn1) is set.
Page 193 CHAPTER 7 TIMER/COUNTER FUNCTION • Capture operation (free-running mode) The following figure illustrates the operation of the capture register when the capture trigger is input. Figure 7-17. CRn1 Capture Operation with Rising Edge Specified Count clock n − 3 n − 2 n −...
Page 194 CHAPTER 7 TIMER/COUNTER FUNCTION (3) Pulse width measurement with free-running counter and two capture registers When 16-bit timer register n (TMn) is used as a free-running counter (refer to Figure 7-19), the pulse width of the signal input to the TIn0 pin can be measured. When the edge specified by bits 4 and 5 (ESn00 and ESn01) of prescaler mode register n0 (PRMn0) is input to the TIn0 pin, the value of TMn is loaded to 16-bit capture/compare register n1 (CRn1), and an external interrupt request signal (INTTMn1) is set.
Page 195 CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-20. Timing of Pulse Width Measurement with Free-Running Counter and Two Capture Registers (with Rising Edge Specified) Count clock TMn count 0000H 0001H D0 + 1 D1 + 1 FFFFH 0000H D2 + 1 value TIn0 pin input Value loaded to CRn1...
Page 196 CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-21. Control Register Settings for Pulse Width Measurement by Restarting (a) 16-bit timer mode control registers 0, 1 (TMC0, TMC1) TMCn3 TMCn2 TMCn1 OVFn TMCn Clears and starts at valid edge of TIn0 pin. (b) Capture/compare control registers 0, 1 (CRC0, CRC1) CRCn2 CRCn1 CRCn0...
Page 197 CHAPTER 7 TIMER/COUNTER FUNCTION 7.2.4 Operation as external event counter TMn can be used as an external event counter that counts the number of clock pulses input to the TIn0 pin from an external source by using 16-bit timer register n (TMn). Each time the valid edge specified by prescaler mode register n0 (PRMn0) has been input, TMn is incremented.
Page 198 CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-24. Configuration of External Event Counter 16-bit capture/compare register n (CRn0) Match INTTMn0 Clear Note Count clock OVFn Selector 16-bit timer/counter n (TMn) Noise eliminator 16-bit capture/compare Valid edge of TIn0 register n1 (CRn1) Internal bus Note The count clock is set by the PRMn0 and PRMn1 registers.
Page 199 CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-26. Control Register Settings in Square Wave Output Mode (a) 16-bit timer mode control registers 0, 1 (TMC0, TMC1) TMCn3 TMCn2 TMCn1 OVFn TMCn Clears and starts on match between TMn and CRn0. (b) Capture/compare control registers 0, 1 (CRC0, CRC1) CRCn2 CRCn1 CRCn0...
Page 200 CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-27. Timing of Square Wave Output Operation Count clock TMn count value N − 1 N − 1 0000H 0001H 0002H 0000H 0001H 0002H 0000H CRn0 INTTMn0 TOn pin output Remark n = 0, 1 7.2.6 Operation to output one-shot pulse TMn can output a one-shot pulse in synchronization with a software trigger and an external trigger (TIn0 pin input).
Page 201 CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-28. Control Register Settings for One-Shot Pulse Output with Software Trigger (a) 16-bit timer mode control registers 0, 1 (TMC0, TMC1) TMCn3 TMCn2 TMCn1 OVFn TMCn Free-running mode (b) Capture/compare control registers 0, 1 (CRC0, CRC1) CRCn2 CRCn1 CRCn0...
Page 202 CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-29. Timing of One-Shot Pulse Output Operation with Software Trigger Sets 0CH to TMCn (TMn count starts) Count clock TMn count 0000H 0001H N + 1 0000H N − 1 M − 1 M + 1 M + 2 value CRn1 set...
Page 203 CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-30. Control Register Settings for One-Shot Pulse Output with External Trigger (a) 16-bit timer mode control registers 0, 1 (TMC0, TMC1) TMCn3 TMCn2 TMCn1 OVFn TMCn Clears and starts at valid edge of TIn0 pin. (b) Capture/compare control registers 0, 1 (CRC0, CRC1) CRCn2 CRCn1...
Page 204 CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-31. Timing of One-Shot Pulse Output Operation with External Trigger (with Rising Edge Specified) Sets 08H to TMCn (TMn count starts) Count clock TMn count 0000H 0001H 0000H N + 1 N + 2 M − 2 M −...
Page 205 CHAPTER 7 TIMER/COUNTER FUNCTION 7.2.7 Cautions (1) Error on starting timer An error of up to 1 clock occurs before the match signal is generated after the timer has been started. This is because 16-bit timer register n (TMn) is started asynchronously to the count pulse. Figure 7-32.
Page 206 CHAPTER 7 TIMER/COUNTER FUNCTION (4) Data hold timing of capture register If the valid edge is input to the TIn0 pin while 16-bit capture/compare register n1 (CRn1) is being read, CRn1 performs the capture operation, but this capture value is not guaranteed. However, the interrupt request signal (INTTMn1) is set as a result of detection of the valid edge.
Page 207 CHAPTER 7 TIMER/COUNTER FUNCTION (7) Operation of OVFn flag (a) OVFn flag set The OVFn flag is set to 1 in the following case: Select a mode in which the timer is cleared and started on a match between TMn and CRn0, a mode in which it is cleared and started by the valid edge of TIn0, or free-running mode.
Page 208 CHAPTER 7 TIMER/COUNTER FUNCTION (c) One-shot pulse output The one-shot pulse output operates correctly only in free-running mode or in clear & start mode at the valid edge of the TIn0 pin. The one-shot pulse cannot be output in the clear & start mode on a match of TMn and CRn0 because an overflow does not occur.
Page 209 CHAPTER 7 TIMER/COUNTER FUNCTION 7.3 8-Bit Timer (TM2 to TM7) 7.3.1 Functions 8-bit timer n has the following two modes (n = 2 to 7). • Mode using timer alone (individual mode) • Mode using the cascade connection (16-bit resolution: cascade connection mode) Caution Do not access following registers when not using the cascade connection.
Page 210 CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-36. Block Diagram of TM2 to TM7 Internal bus 8-bit compare Selector register n (CRn0) INTTMn Mask Match circuit Note 2 8-bit counter n Selector Selector Note 1 (TMn) Count clock Clear Invert level Selector TCEn TMCn6 TMCn4 LVSm LVRm TMCm1 TOEm...
Page 211 CHAPTER 7 TIMER/COUNTER FUNCTION (1) 8-bit counters 2 to 7 (TM2 to TM7) TMn is an 8-bit read-only register that counts the count pulses. The counter is incremented synchronous to the rising edge of the count clock. TM2 and TM3 or TM5 and TM6 can be connected in cascade and used as 16-bit timers. When TMm and TMm+1 are connected in cascade and used as a 16-bit timer, they can be read by a 16-bit memory manipulation instruction.
Page 212 CHAPTER 7 TIMER/COUNTER FUNCTION 7.3.3 Timer n control register The following two types of registers control timer n. • Timer clock selection registers n0, n1 (TCLn0, TCLn1) • 8-bit timer mode control register n (TMCn) (1) Timer clock selection registers 20 to 71 and 21 to 71 (TCL20 to TCL70 and TCL21 to TCL71) These registers set the count clock of timer n.
Page 213 CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-37. TM2, TM3 Timer Clock Selection Registers 20, 21, 30, 31 (TCL20, TCL21, TCL30, and TCL31) After reset: 00H Address: FFFFF244H, FFFFF254H TCLn0 TCLn2 TCLn1 TCLn0 (n = 2, 3) After reset: 00H Address: FFFFF24EH, FFFFF25EH TCLn1 TCLn3 (n = 2, 3)
Page 214 CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-38. TM4, TM5 Timer Clock Selection Registers 40, 41, 50, 51 (TCL40, TCL41, TCL50, and TCL51) After reset: 00H Address: FFFFF264H, FFFFF274H TCLn0 TCLn2 TCLn1 TCLn0 (n = 4, 5) After reset: 00H Address: FFFFF26EH, FFFFF27EH TCLn1 TCLn3 (n = 4, 5)
Page 215 CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-39. TM6, TM7 Timer Clock Selection Registers 60, 61, 70, 71 (TCL60, TCL61, TCL70, and TCL71) After reset: 00H Address: FFFFF284H, FFFFF294H TCLn0 TCLn2 TCLn1 TCLn0 (n = 6, 7) After reset: 00H Address: FFFFF28EH, FFFFF29EH TCLn1 TCLn3 (n = 6, 7)
Page 216 CHAPTER 7 TIMER/COUNTER FUNCTION (2) 8-bit timer mode control registers 2 to 7 (TMC2 to TMC7) The TMCn register makes the following six settings. (1) Controls the counting by 8-bit counter n (TMn) (2) Selects the operating mode of 8-bit counter n (TMn) (3) Selects the individual mode or cascade connection mode (4) Sets the state of the timer output flip-flop (5) Controls the timer flip-flop or selects the active level in the PWM (free-running) mode...
Page 217 CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-40. 8-Bit Timer Mode Control Registers 2 to 7 (TMC2 to TMC7) After reset: Address: TMC2 FFFFF246H TMC5 FFFFF276H TMC3 FFFFF256H TMC6 FFFFF286H TMC4 FFFFF266H TMC7 FFFFF296H <7> <3> <2> <0> TMCn TMCn6 TCEn TMCn4 LVSm LVRm TMCm1...
Page 218 CHAPTER 7 TIMER/COUNTER FUNCTION 7.4 8-Bit Timer Operation 7.4.1 Operation as an interval timer (8-bit operation) The timer operates as an interval timer that repeatedly generates interrupts at the interval of the preset count in 8- bit compare register n (CRn0). If the count in 8-bit counter n (TMn) matches the value set in CRn0, simultaneous to clearing the value of TMn to 0 and continuing the count, the interrupt request signal (INTTMn) is generated.
Page 219 CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-41. Timing of Interval Timer Operation (2/3) When CRn0 = 00H Count clock TMn 00H CRn0 TCEn INTTMn Interval time Remark n = 2 to 7 When CRn0 = FFH Count clock CRn0 TCEn INTTMn Interrupt acknowledgement Interrupt acknowledgement Interval time...
Page 220 CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-41. Timing of Interval Timer Operation (3/3) Operated by CRn0 transition (M < N) Count clock CRn0 TCEn INTTMn TMn overflows since M < N CRn0 transition Remark n = 2 to 7 Operated by CRn0 transition (M > N) Count clock N −...
Page 221 CHAPTER 7 TIMER/COUNTER FUNCTION 7.4.2 Operation as external event counter The external event counter counts the number of external clock pulses that are input to TIn. Each time a valid edge specified with timer clock selection register n0, n1 (TCLn0, TCLn1) is input, TMn is incremented.
Page 222 CHAPTER 7 TIMER/COUNTER FUNCTION 7.4.3 Operation as square wave output (8-bit resolution) A square wave having any frequency is output at the interval preset in 8-bit compare register n (CRn0). By setting bit 0 (TOEn) of 8-bit timer mode control register n (TMCn) to 1, the output state of TOn is inverted with the count preset in CRn0 as the interval.
Page 223 CHAPTER 7 TIMER/COUNTER FUNCTION 7.4.4 Operation as 8-bit PWM output By setting bit 6 (TMCn6) of 8-bit timer mode control register n (TMCn) to 1, the timer operates as a PWM output. Pulses with the duty factor determined by the value set in 8-bit compare register n (CRn0) are output from TOn. Set the width of the active level of the PWM pulse in CRn0.
Page 224 CHAPTER 7 TIMER/COUNTER FUNCTION (1) Basic operation of the PWM output Setting method (1) Set the port latch and port mode register n to 0. (2) Set the active level width in 8-bit compare register n (CRn0). (3) Select the count clock with timer clock selection register n0, n1 (TCLn0, TCLn1). (4) Set the active level in bit 1 (TMCn1) of TMCn.
Page 225 CHAPTER 7 TIMER/COUNTER FUNCTION Basic operation of PWM output Figure 7-44. Timing of PWM Output Basic operation (active level = H) Count clock N + 1 CRn0 TCEn INTTMn Active level Inactive level Active level When CRn0 = 0 Count clock 00H 01H N + 1 N + 2 CRn0...
Page 226 CHAPTER 7 TIMER/COUNTER FUNCTION Operation based on CRn0 transitions Figure 7-45. Timing of Operation Based on CRn0 Transitions When the CRn0 value changes from N to M before TMn overflows Count clock N + 1 N + 2 M + 1 M + 2 M + 1 M + 2...
Page 227 CHAPTER 7 TIMER/COUNTER FUNCTION 7.4.5 Operation as interval timer (16 bits) (1) Cascade connection (16-bit timer) mode The V850/SB1 and V850/SB2 provide a 16-bit register that can be used when connecting in cascade. The available registers are as follows. TM2, TM3 cascade connection: 16-bit counter TM23 (Address: FFFFF24AH) 16-bit compare register CR23 (Address: FFFFF24CH) TM4, TM5 cascade connection:...
Page 228 CHAPTER 7 TIMER/COUNTER FUNCTION A timing example of the cascade connection mode with 16-bit resolution is shown below. Figure 7-46. Cascade Connection Mode with 16-Bit Resolution Count clock N + 1 TMn + 1 M − 1 CRn0 CR(n+1)0 TCEn TCEn + 1 INTTMn Interval time...
Page 229 CHAPTER 7 TIMER/COUNTER FUNCTION 7.4.6 Cautions (1) Error when the timer starts The time until the match signal is generated after the timer starts has a maximum error of one clock. The reason is the starting of 8-bit counter n (TMn) is asynchronous with respect to the count pulse. Figure 7-47.
Page 230 CHAPTER 8 WATCH TIMER 8.1 Function The watch timer has the following functions: • Watch timer • Interval timer The watch timer and interval timer functions can be used at the same time. Figure 8-1. Block Diagram of Watch Timer Clear 5-bit counter INTWTN...
Page 231 CHAPTER 8 WATCH TIMER (1) Watch timer The watch timer generates an interrupt request (INTWTN) at time intervals of 0.5 seconds or 0.25 seconds by using the main system clock or subsystem clock. (2) Interval timer The watch timer generates an interrupt request (INTWTNI) at time intervals specified in advance. Table 8-1.
Page 232 CHAPTER 8 WATCH TIMER 8.3 Watch Timer Control Register The watch timer mode control register (WTNM) and watch timer clock selection register (WTNCS) control the watch timer. The watch timer should be operated after setting the count clock and interval time. (1) Watch timer mode control register (WTNM) This register enables or disables the count clock and operation of the watch timer, sets the interval time of the prescaler, controls the operation of the 5-bit counter, and sets the set time of the watch flag.
Page 233 CHAPTER 8 WATCH TIMER Remarks 1. f : Watch timer clock frequency 2. Values in parentheses apply when f = 32.768 kHz. 3. For the settings of WTNM7, refer to Figure 8-3. (2) Watch timer clock selection register (WTNCS) This register selects the count clock of the watch timer. WTNCS is set using an 8-bit memory manipulation instruction.
Page 234 CHAPTER 8 WATCH TIMER 8.4 Operation 8.4.1 Operation as watch timer The watch timer operates with time intervals of 0.5 seconds with the subsystem clock (32.768 kHz). The watch timer generates an interrupt request at fixed time intervals. The count operation of the watch timer is started when bits 0 (WTNM0) and 1 (WTNM1) of the watch timer mode control register (WTNM) are set to 1.
Page 235 CHAPTER 8 WATCH TIMER Figure 8-4. Operation Timing of Watch Timer/Interval Timer 5-bit counter Overflow Overflow Start Count clock f Watch timer interrupt INTWTN Interrupt time of watch timer (0.5 s) Interrupt time of watch timer (0.5 s) Interval timer interrupt INTWTNI Interval time Interval time...
Page 236 CHAPTER 9 WATCHDOG TIMER 9.1 Functions The watchdog timer has the following functions. • Watchdog timer • Interval timer • Selecting the oscillation stabilization time Caution Use the watchdog timer mode register (WDTM) to select the watchdog timer mode or the interval timer mode.
Page 237 CHAPTER 9 WATCHDOG TIMER (1) Watchdog timer mode This mode detects inadvertent program loop. When inadvertent program loop is detected, a non-maskable interrupt can be generated. Table 9-1. Inadvertent Program Loop Detection Time of Watchdog Timer Clock Inadvertent Program Loop Detection Time Note = 20 MHz = 12.58 MHz...
Page 238 CHAPTER 9 WATCHDOG TIMER 9.2 Configuration The watchdog timer includes the following hardware. Table 9-3. Configuration of Watchdog Timer Item Configuration Control registers Oscillation stabilization time selection register (OSTS) Watchdog timer clock selection register (WDCS) Watchdog timer mode register (WDTM) 9.3 Watchdog Timer Control Register The registers to control the watchdog timer is shown below.
Page 239 CHAPTER 9 WATCHDOG TIMER (2) Watchdog timer clock selection register (WDCS) This register selects the overflow times of the watchdog timer and the interval timer. WDCS is set by an 8-bit memory manipulation instruction. RESET input clears WDCS to 00H. Figure 9-3.
Page 240 CHAPTER 9 WATCHDOG TIMER (3) Watchdog timer mode register (WDTM) This register sets the operating mode of the watchdog timer, and enables and disables counting. WDTM is set by an 8-/1-bit memory manipulation instruction. RESET input clears WDTM to 00H. Figure 9-4.
Page 241 CHAPTER 9 WATCHDOG TIMER 9.4 Operation 9.4.1 Operation as watchdog timer Set bit 4 (WDTM4) of the watchdog timer mode register (WDTM) to 1 to operate as a watchdog timer to detect an inadvertent program loop. Setting bit 7 (RUN) of WDTM to 1 starts the count. After counting starts, if RUN is set to 1 again within the set time interval for inadvertent program loop detection, the watchdog timer is cleared and counting starts again.
Page 242 CHAPTER 9 WATCHDOG TIMER 9.4.2 Operation as interval timer Set bit 4 (WDTM4) to 0 in the watchdog timer mode register (WDTM) to operate the watchdog timer as an interval timer that repeatedly generates interrupts with a preset count value as the interval. When operating as an interval timer, the interrupt mask flag (WDTMK) of the WDTIC register and the priority setting flag (WDTPR0 to WDTPR2) become valid, and a maskable interrupt (INTWDTM) can be generated.
Page 243 CHAPTER 9 WATCHDOG TIMER 9.5 Standby Function Control Register The wait time from releasing the stop mode until the oscillation stabilizes is controlled by the oscillation stabilization time selection register (OSTS). OSTS is set by an 8-bit memory manipulation instruction. RESET input sets OSTS to 04H.
Page 244 CHAPTER 10 SERIAL INTERFACE FUNCTION 10.1 Overview The V850/SB1 and V850/SB2 incorporate the following serial interfaces. Note • Channel 0: 3-wire serial I/O (CSI0)/I • Channel 1: 3-wire serial I/O (CSI1)/Asynchronous serial interface (UART0) Note • Channel 2: 3-wire serial I/O (CSI2)/I •...
Page 245 CHAPTER 10 SERIAL INTERFACE FUNCTION 10.2.1 Configuration CSIn includes the following hardware. Table 10-1. Configuration of CSIn Item Configuration Registers Serial I/O shift registers 0 to 3 (SIO0 to SIO3) Control registers Serial operation mode registers 0 to 3 (CSIM0 to CSIM3) Serial clock selection registers 0 to 3 (CSIS0 to CSIS3) Figure 10-1.
Page 246 CHAPTER 10 SERIAL INTERFACE FUNCTION 10.2.2 CSIn control registers CSIn uses is controlled by the following registers. • Serial operation mode register n (CSIMn) • Serial clock selection register n (CSISn) (1) Serial operation mode registers 0 to 3 (CSIM0 to CSIM3) CSIMn is used to enable or disable serial interface channel n’s serial clock, operation modes, and specific operations.
Page 247 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-2. Serial Operation Mode Registers 0 to 3 (CSIM0 to CSIM3) After reset: Address: CSIM0 FFFFF2A2H CSIM1 FFFFF2B2H CSIM2 FFFFF2C2H CSIM3 FFFFF2D2H <7> CSIMn CSIEn MODEn SCLn1 SCLn0 (n = 0 to 3) CSIEn SIOn operation enable/disable specification Shift register operation Serial counter...
Page 248 CHAPTER 10 SERIAL INTERFACE FUNCTION (2) Serial clock selection registers 0 to 3 (CSIS0 to CSIS3) CSISn is used to set serial interface channel n’s serial clock. CSISn can be set by an 8-bit memory manipulation instruction. RESET input clears these registers to 00H. Figure 10-3.
Page 249 CHAPTER 10 SERIAL INTERFACE FUNCTION 10.2.3 Operations CSIn has the following two operation modes. • Operation stop mode • 3-wire serial I/O mode (1) Operation stop mode This mode does not perform serial transfers and can therefore reduce power consumption. When in operation stop mode, if SIn, SOn, and SCKn pin are also used as I/O ports, they can be used as normal I/O ports as well.
Page 250 CHAPTER 10 SERIAL INTERFACE FUNCTION (2) 3-wire serial I/O mode 3-wire serial I/O mode is useful when connecting to a peripheral I/O device that includes a clocked serial interface, a display controller, etc. This mode executes data transfers via three lines: a serial clock line (SCKn), serial output line (SOn), and serial input line (SIn).
Page 251 CHAPTER 10 SERIAL INTERFACE FUNCTION (b) Communication operations In 3-wire serial I/O mode, data is transmitted and received in 8-bit units. Each bit of data is sent or received in synchronization with the serial clock. Serial I/O shift register n (SIOn) is shifted in synchronization with the falling edge of the serial clock. Transmission data is held in the SOn latch and is output from the SOn pin.
Page 252 CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3 I C Bus To use the I C bus function, set the P10/SDA0, P12/SCL0, P20/SDA1, and P22/SCL1 pins to N-ch open drain output. The products with an on-chip I C bus are shown below. •...
Page 253 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-7. Block Diagram of I Internal bus IIC status register n (IICSn) MSTSn ALDn EXCn COIn TRCn ACKDn STDn SPDn IIC control register n (IICCn) Slave address register n (SVAn) IICEn LRELn WRELn SPIEn WTIMn ACKEn STTn SPTn SDAn Match...
Page 254 CHAPTER 10 SERIAL INTERFACE FUNCTION A serial bus configuration example is shown below. Figure 10-8. Serial Bus Configuration Example Using I C Bus Master CPU1 Master CPU2 Serial data bus Slave CPU2 Slave CPU1 Serial clock Address 1 Address 2 Slave CPU3 Address 3 Slave IC...
Page 255 CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3.1 Configuration Cn includes the following hardware (n = 0, 1). Table 10-2. Configuration of I Item Configuration Registers IIC shift registers 0 and 1 (IIC0, IIC1) Slave address registers 0 and 1 (SVA0, SVA1) Control registers IIC control registers 0 and 1 (IICC0, IICC1) IIC status registers 0 and 1 (IICS0, IICS1)
Page 256 CHAPTER 10 SERIAL INTERFACE FUNCTION (7) Interrupt request signal generator This circuit controls the generation of interrupt request signals (INTIICn). An I C interrupt is generated following either of two triggers. Note • Eighth or ninth clock of the serial clock (set by WTIMn bit Note •...
Page 257 CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3.2 I C control register C0 and I C1 are controlled by the following registers. • IIC control registers 0, 1 (IICC0, IICC1) • IIC status registers 0, 1 (IICS0, IICS1) • IIC clock selection registers 0, 1 (IICCL0, IICCL1) •...
Page 258 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-9. IIC Control Register n (IICCn) (1/4) After reset: 00H Address: FFFFF340H, FFFFF350H <7> <6> <5> <4> <3> <2> <1> <0> IICCn IICEn LRELn WRELn SPIEn WTIMn ACKEn STTn SPTn (n = 0, 1) IICEn Cn operation enable/disable specification Stops operation.
Page 259 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-9. IIC Control Register n (IICCn) (2/4) After reset: 00H Address: FFFFF340H, FFFFF350H <7> <6> <5> <4> <3> <2> <1> <0> IICCn IICEn LRELn WRELn SPIEn WTIMn ACKEn STTn SPTn (n = 0, 1) WRELn Wait cancellation control Does not cancel wait...
Page 260 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-9. IIC Control Register n (IICCn) (3/4) After reset: 00H Address: FFFFF340H, FFFFF350H <7> <6> <5> <4> <3> <2> <1> <0> IICCn IICEn LRELn WRELn SPIEn WTIMn ACKEn STTn SPTn (n = 0, 1) ACKEn Acknowledge control Disable acknowledge.
Page 261 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-9. IIC Control Register n (IICCn) (4/4) After reset: 00H Address: FFFFF340H, FFFFF350H <7> <6> <5> <4> <3> <2> <1> <0> IICCn IICEn LRELn WRELn SPIEn WTIMn ACKEn STTn SPTn (n = 0, 1) SPTn Stop condition trigger Stop condition is not generated.
Page 262 CHAPTER 10 SERIAL INTERFACE FUNCTION (2) IIC status registers 0, 1 (IICS0, IICS1) IICSn indicates the status of the I Cn bus. IICSn can be set by an 8-/1-bit memory manipulation instruction. IICSn is a read-only register (n = 0, 1). RESET input sets IICSn to 00H.
Page 263 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-10. IIC Status Register n (IICSn) (2/3) After reset: 00H Address: FFFFF342H, FFFFF352H <7> <6> <5> <4> <3> <2> <1> <0> IICSn MSTSn ALDn EXCn COIn TRCn ACKDn STDn SPDn (n = 0, 1) EXCn Detection of extension code reception Extension code was not received.
Page 264 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-10. IIC Status Register n (IICSn) (3/3) After reset: 00H Address: FFFFF342H, FFFFF352H <7> <6> <5> <4> <3> <2> <1> <0> IICSn MSTSn ALDn EXCn COIn TRCn ACKDn STDn SPDn (n = 0, 1) ACKDn Detection of ACK ACK was not detected.
Page 265 CHAPTER 10 SERIAL INTERFACE FUNCTION (3) IIC clock selection registers 0, 1 (IICCL0, IICCL1) IICCLn is used to set the transfer clock for the I Cn bus. IICCLn can be set by an 8-/1-bit memory manipulation instruction. Bits SMCn, CLn1 and CLn0 are set using CLXn bit of IIC function expansion register n (IICXn) in combination with bits IICCEn1 and IICCEn0 of IIC clock expansion register n (IICCEn) (n = 0, 1) (see 10.3.2 (6) I Cn transfer clock setting method).
Page 266 CHAPTER 10 SERIAL INTERFACE FUNCTION (4) IIC function expansion registers 0, 1 (IICX0, IICX1) These registers set the function expansion of I Cn (valid only in high-speed mode). IICXn is set with a 1-/8-bit memory manipulation instruction. Set the CLXn bit in combination with the SMCn, DFCn, CLn1, and the CLn0 bits of IIC clock selection register n (IICCLn) and the IICCEn1 and IICCEn0 bits of IIC clock expansion register n (IICCEn) (see 10.3.2 (6) I Cn transfer clock setting method) (n = 0, 1).
Page 267 CHAPTER 10 SERIAL INTERFACE FUNCTION m x T + t m/2 x T m/2 x T SCLn SCLn inversion SCLn inversion SCLn inversion The selection clock is set using a combination of the SMCn, CLn1, and CLn0 bits of IIC clock selection register n (IICCLn), the CLXn bit of IIC function expansion register n (IICXn), and IICCEn1 and the IICCEn0 bits of IIC clock expansion register n (IICCEn) (n = 0, 1).
Page 268 CHAPTER 10 SERIAL INTERFACE FUNCTION (7) IIC shift registers 0, 1 (IIC0, IIC1) IICn is used for serial transmission/reception (shift operations) that is synchronized with the serial clock. It can be read from or written to in 8-bit units, but data should not be written to IICn during a data transfer (n = 0, 1). Figure 10-14.
Page 269 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-16. Pin Configuration Diagram Slave device Master device Clock output (Clock output) (Clock input) Clock input Data output Data output Data input Data input 10.3.4 I C bus definitions and control methods The following section describes the I C bus’s serial data communication format and the signals used by the I bus.
Page 270 CHAPTER 10 SERIAL INTERFACE FUNCTION Start condition A start condition is met when the SCLn pin is at high level and the SDAn pin changes from high level to low level. The start conditions for the SCLn pin and SDAn pin are signals that the master device outputs to the slave device when starting a serial transfer.
Page 271 CHAPTER 10 SERIAL INTERFACE FUNCTION The slave address and the eighth bit, which specifies the transfer direction as described in (3) Transfer direction specification below, are together written to the IIC shift register (IICn) and are then output. Received addresses are written to IICn (n = 0, 1). The slave address is assigned to the higher 7 bits of IICn.
Page 272 CHAPTER 10 SERIAL INTERFACE FUNCTION Acknowledge signal (ACK) The acknowledge signal (ACK) is used by the transmitting and receiving devices to confirm serial data reception. The receiving device returns one ACK signal for each 8 bits of data it receives. The transmitting device normally receives an ACK signal after transmitting 8 bits of data.
Page 273 CHAPTER 10 SERIAL INTERFACE FUNCTION When the local address is received, an ACK signal is automatically output in synchronization with the falling edge of the SCLn’s eighth clock regardless of the ACKEn value. No ACK signal is output if the received address is not a local address (n = 0, 1).
Page 274 CHAPTER 10 SERIAL INTERFACE FUNCTION Wait signal (WAIT) The wait signal (WAIT) is used to notify the communication partner that a device (master or slave) is preparing to transmit or receive data (i.e., is in a wait state). Setting the SCLn pin to low level notifies the communication partner of the wait status. When wait status has been canceled for both the master and slave devices, the next data transfer can begin (n = 0, 1).
Page 275 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-23. Wait Signal (2/2) (b) When master and slave devices both have a nine-clock wait (master: transmission, slave: reception, and ACKEn = 1) Master and slave both wait Master after output of ninth clock. IIC0 data write (cancel wait) IIC0 Slave...
Page 276 CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3.5 I C interrupt requests (INTIICn) The following shows the value of IIC status register n (IICSn) at the INTIICn interrupt request generation timing and at the INTIICn interrupt timing (n = 0, 1). (1) Master device operation (a) Start ~ Address ~ Data ~ Data ~ Stop (normal transmission/reception) <1>...
Page 277 CHAPTER 10 SERIAL INTERFACE FUNCTION (b) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (restart) <1> When WTIMn = 0 STTn = 1 SPTn = 1 ↓ ↓ AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 ∆7 L1: IICSn = 10XXX110B...
Page 278 CHAPTER 10 SERIAL INTERFACE FUNCTION (c) Start ~ Code ~ Data ~ Data ~ Stop (extension code transmission) <1> When WTIMn = 0 SPTn = 1 ↓ AD6 to AD0 D7 to D0 D7 to D0 ∆5 L1: IICSn = 1010X110B L2: IICSn = 1010X000B L3: IICSn = 1010X000B (WTIMn = 1) L4: IICSn = 1010XX00B...
Page 279 CHAPTER 10 SERIAL INTERFACE FUNCTION (2) Slave device operation (when receiving slave address data (match with SVAn)) (a) Start ~ Address ~ Data ~ Data ~ Stop <1> When WTIMn = 0 AD6 to AD0 D7 to D0 D7 to D0 ∆4 L1: IICSn = 0001X110B L2: IICSn = 0001X000B...
Page 280 CHAPTER 10 SERIAL INTERFACE FUNCTION (b) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn = 0 (after restart, match with SVAn) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 ∆5 L1: IICSn = 0001X110B L2: IICSn = 0001X000B...
Page 281 CHAPTER 10 SERIAL INTERFACE FUNCTION (c) Start ~ Address ~ Data ~ Start ~ Code ~ Data ~ Stop <1> When WTIMn = 0 (after restart, extension code reception) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 ∆5 L1: IICSn = 0001X110B L2: IICSn = 0001X000B...
Page 282 CHAPTER 10 SERIAL INTERFACE FUNCTION (d) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn = 0 (after restart, mismatch with address (= not extension code)) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 ∆4 L1: IICSn = 0001X110B...
Page 283 CHAPTER 10 SERIAL INTERFACE FUNCTION (3) Slave device operation (when receiving extension code) (a) Start ~ Code ~ Data ~ Data ~ Stop <1> When WTIMn = 0 AD6 to AD0 D7 to D0 D7 to D0 ∆4 L1: IICSn = 0010X010B L2: IICSn = 0010X000B L3: IICSn = 0010X000B ∆...
Page 284 CHAPTER 10 SERIAL INTERFACE FUNCTION (b) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn = 0 (after restart, match with SVAn) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 ∆5 L1: IICSn = 0010X010B L2: IICSn = 0010X000B...
Page 285 CHAPTER 10 SERIAL INTERFACE FUNCTION (c) Start ~ Code ~ Data ~ Start ~ Code ~ Data ~ Stop <1> When WTIMn = 0 (after restart, extension code reception) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 ∆5 L1: IICSn = 0010X010B L2: IICSn = 0010X000B...
Page 286 CHAPTER 10 SERIAL INTERFACE FUNCTION (d) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn = 0 (after restart, mismatch with address (= not extension code)) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 ∆4 L1: IICSn = 0010X010B...
Page 287 CHAPTER 10 SERIAL INTERFACE FUNCTION (4) Operation without communication (a) Start ~ Code ~ Data ~ Data ~ Stop AD6 to AD0 D7 to D0 D7 to D0 ∆1 ∆ 1: IICSn = 00000001B ∆: Generated only when SPIEn = 1 Remark n = 0, 1 (5) Arbitration loss operation (operation as slave after arbitration loss)
Page 288 CHAPTER 10 SERIAL INTERFACE FUNCTION (b) When arbitration loss occurs during transmission of extension code <1> When WTIMn = 0 AD6 to AD0 D7 to D0 D7 to D0 ∆4 L1: IICSn = 0110X010B (Example: when ALDn is read during interrupt servicing) L2: IICSn = 0010X000B L3: IICSn = 0010X000B ∆...
Page 289 CHAPTER 10 SERIAL INTERFACE FUNCTION (6) Operation when arbitration loss occurs (no communication after arbitration loss) (a) When arbitration loss occurs during transmission of slave address data AD6 to AD0 D7 to D0 D7 to D0 ∆2 L1: IICSn = 01000110B (Example: when ALDn is read during interrupt servicing) ∆...
Page 290 CHAPTER 10 SERIAL INTERFACE FUNCTION (c) When arbitration loss occurs during data transfer <1> When WTIMn = 0 AD6 to AD0 D7 to D0 D7 to D0 ∆3 L1: IICSn = 10001110B L2: IICSn = 01000000B (Example: when ALDn is read during interrupt servicing) ∆...
Page 291 CHAPTER 10 SERIAL INTERFACE FUNCTION (d) When loss occurs due to restart condition during data transfer <1> Not extension code (Example: mismatches with SVAn) AD6 to AD0 D7 to Dn AD6 to AD0 D7 to D0 ∆3 L1: IICSn = 1000X110B L2: IICSn = 01000110B (Example: when ALDn is read during interrupt servicing) ∆...
Page 292 CHAPTER 10 SERIAL INTERFACE FUNCTION (e) When loss occurs due to stop condition during data transfer AD6 to AD0 D7 to Dn ∆2 L1: IICSn = 1000X110B ∆ 2: IICSn = 01000001B L: Always generated Remark ∆: Generated only when SPIEn = 1 X: don’t care Dn = D6 to D0 n = 0, 1...
Page 293 CHAPTER 10 SERIAL INTERFACE FUNCTION (g) When arbitration loss occurs due to a stop condition when attempting to generate a restart condition When WTIMn = 1 STTn = 1 ↓ AD6 to AD0 D7 to D0 ∆3 L1: IICSn = 1000X110B L2: IICSn = 1000XX00B ∆...
Page 294 CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3.6 Interrupt request (INTIICn) generation timing and wait control The setting of bit 3 (WTIMn) in IIC control register n (IICCn) determines the timing by which INTIICn is generated and the corresponding wait control, as shown below (n = 0, 1). Table 10-4.
Page 295 CHAPTER 10 SERIAL INTERFACE FUNCTION Stop condition detection INTIICn is generated when a stop condition is detected. Remark n = 0, 1 10.3.7 Address match detection method When in I C bus mode, the master device can select a particular slave device by transmitting the corresponding slave address.
Page 296 CHAPTER 10 SERIAL INTERFACE FUNCTION Table 10-5. Extension Code Bit Definitions Slave Address R/W Bit Description 0000 General call address 0000 Start byte 0000 CBUS address 0000 Address that is reserved for different bus format 1111 10-bit slave address specification 10.3.10 Arbitration When several master devices simultaneously output a start condition (when STTn is set to 1 before STDn is set to Note...
Page 297 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-24. Arbitration Timing Example Master 1 Hi-Z Hi-Z Master 1 loses arbitration Master 2 Transfer lines Remark n = 0, 1 Table 10-6. Status During Arbitration and Interrupt Request Generation Timing Status During Arbitration Interrupt Request Generation Timing Note 1 At falling edge of eighth or ninth clock following byte transfer...
Page 298 CHAPTER 10 SERIAL INTERFACE FUNCTION Notes 1. When WTIMn (bit 3 of the IIC control register n (IICCn)) = 1, an interrupt request occurs at the falling edge of the ninth clock. When WTIMn = 0 and the extension code’s slave address is received, an interrupt request occurs at the falling edge of the eighth clock (n = 0, 1).
Page 299 CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3.12 Communication reservation To start master device communications when not currently using a bus, a communication reservation can be made to enable transmission of a start condition when the bus is released. There are two modes under which the bus is not used.
Page 300 CHAPTER 10 SERIAL INTERFACE FUNCTION The communication reservation timing is shown below. Figure 10-25. Communication Reservation Timing Write to Program processing IIC0 Set SPD Communication Hardware processing reservation and INTIIC0 Output by master with bus access IICn: IIC shift register n STTn: Bit 1 of IIC control register n (IICCn) STDn:...
Page 301 CHAPTER 10 SERIAL INTERFACE FUNCTION The communication reservation flow chart is illustrated below. Figure 10-27. Communication Reservation Flow Chart SET1 STTn ; Sets STT flag (communication reservation). Define communication ; Defines that communication reservation is in effect reservation (defines and sets user flag to any part of RAM). ;...
Page 302 CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3.13 Cautions After a reset, when changing from a mode in which no stop condition has been detected (the bus has not been released) to a master device communication mode, first generate a stop condition to release the bus, then perform master device communication.
Page 303 CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3.14 Communication operations Master operations The following is a flow chart of the master operations. Figure 10-28. Master Operation Flow Chart START ← ××H IICCLn Select transfer clock. ← ××H IICCn IICEn = SPIEn = WTIMn = 1 INTIICn = 1? Start IICn write transfer.
Page 304 CHAPTER 10 SERIAL INTERFACE FUNCTION Slave operation An example of slave operation is shown below. Figure 10-29. Slave Operation Flow Chart START ← ××H IICCn IICEn = 1 INTIICn = 1? EXCn = 1? Communicate? COIn = 1? LRELn = 1 TRCn = 1? WTIMn = 0 ACKEn = 1...
Page 305 CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3.15 Timing of data communication When using I C bus mode, the master device outputs an address via the serial bus to select one of several slave devices as its communication partner. After outputting the slave address, the master device transmits the TRCn bit (bit 3 of IIC status register n (IICSn)) that specifies the data transfer direction and then starts serial communication with the slave device.
Page 306 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-30. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (1/3) (a) Start condition ~ address Processing by master device ← ← IICn IICn address IICn data ACKDn STDn SPDn...
Page 307 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-30. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (2/3) (b) Data Processing by master device ← ← IICn IICn data IICn data ACKDn STDn SPDn WTIMn ACKEn MSTSn...
Page 308 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-30. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (3/3) (c) Stop condition Processing by master device ← ← IICn IICn data IICn address ACKDn STDn SPDn WTIMn ACKEn...
Page 309 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-31. Example of Slave to Master Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (1/3) (a) Start condition ~ address Processing by master device ← ← IICn IICn address IICn FFH Note ACKDn STDn SPDn...
Page 310 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-31. Example of Slave to Master Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (2/3) (b) Data Processing by master device IICn ← FFH Note IICn ← FFH Note IICn ACKDn STDn SPDn WTIMn...
Page 311 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-31. Example of Slave to Master Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (3/3) (c) Stop condition Processing by master device ← ← IICn IICn FFH Note IICn address ACKDn STDn SPDn WTIMn...
Page 312 CHAPTER 10 SERIAL INTERFACE FUNCTION 10.4 Asynchronous Serial Interface (UART0, UART1) UARTn (n = 0, 1) has the following two operation modes. (1) Operation stop mode This mode is used when serial transfers are not performed. It can therefore be used to reduce power consumption.
Page 313 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-32. Block Diagram of UARTn Internal bus Receive buffer registers 0, 1 (RXB0, RXB1) Receive shift registers RXD0, RXD1 0, 1 (RX0, RX1) Transmit shift registers TXD0, TXD1 0, 1 (TXS0, TXS1) Receive control INTSR0, parity check INTSR1...
Page 314 CHAPTER 10 SERIAL INTERFACE FUNCTION (4) Transmission controller The transmission controller controls transmit operations, such as adding a start bit, parity bit, and stop bit to data that is written to transmit shift register n (TXSn), based on the values set to asynchronous serial interface mode register n (ASIMn).
Page 315 CHAPTER 10 SERIAL INTERFACE FUNCTION (1) Asynchronous serial interface mode registers 0, 1 (ASIM0, ASIM1) ASIMn is an 8-bit register that controls UARTn’s serial transfer operations. ASIMn can be set by an 8-/1-bit memory manipulation instruction. RESET input clears these registers to 00H. Figure 10-33.
Page 316 CHAPTER 10 SERIAL INTERFACE FUNCTION (2) Asynchronous serial interface status registers 0, 1 (ASIS0, ASIS1) When a receive error occurs in asynchronous serial interface mode, these registers indicate the type of error. ASISn can be read using an 8-/1-bit memory manipulation instruction. RESET input clears these registers to 00H.
Page 317 CHAPTER 10 SERIAL INTERFACE FUNCTION (3) Baud rate generator control registers 0, 1 (BRGC0, BRGC1) These registers set the serial clock for UARTn. BRGCn can be set by an 8-bit memory manipulation instruction. RESET input clears these registers to 00H. Figure 10-35.
Page 318 CHAPTER 10 SERIAL INTERFACE FUNCTION (4) Baud rate generator mode control registers n0, n1 (BRGMCn0, BRGMCn1) These registers set the UARTn source clock. BRGMCn0 and BRGMCn1 are set by an 8-bit memory manipulation instruction. RESET input clears these registers to 00H. Figure 10-36.
Page 319 CHAPTER 10 SERIAL INTERFACE FUNCTION 10.4.3 Operations UARTn has the following two operation modes. • Operation stop mode • Asynchronous serial interface mode (1) Operation stop mode In this mode serial transfers are not performed, allowing reduction in power consumption. When in operation stop mode, pins can be used as ordinary ports.
Page 320 CHAPTER 10 SERIAL INTERFACE FUNCTION (2) Asynchronous serial interface mode This mode enables full-duplex operation, in which one byte of data is transmitted and received after the start bit. The on-chip dedicated UARTn baud rate generator enables communications using a wide range of selectable baud rates.
Page 321 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-39. ASISn Setting (Asynchronous Serial Interface Mode) After reset: 00H Address: FFFFF302H, FFFFF312H ASISn OVEn (n = 0, 1) Parity error flag No parity error Parity error (Transmit data parity does not match) Framing error flag No framing error Note 1 Framing error...
Page 322 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-40. BRGCn Setting (Asynchronous Serial Interface Mode) After reset: 00H Address: FFFFF304H, FFFFF314H BRGCn MDLn7 MDLn6 MDLn5 MDLn4 MDLn3 MDLn2 MDLn1 MDLn0 (n = 0, 1) Input clock selection × × × − Setting prohibited •...
Page 323 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-41. BRGMCn0 and BRGMCn1 Settings (Asynchronous Serial Interface Mode) After reset: 00H Address: FFFFF30EH, FFFFF31EH BRGMCn0 TPSn2 TPSn1 TPSn0 (n = 0, 1) After reset: 00H Address: FFFFF320H, FFFFF322H BRGMCn1 TPSn3 (n = 0, 1) TPSn3 TPSn2 TPSn1...
Page 324 CHAPTER 10 SERIAL INTERFACE FUNCTION (b) Baud rate The baud rate transmit/receive clock that is generated is obtained by dividing the main clock. • Generation of baud rate transmit/receive clock using main clock The transmit/receive clock is obtained by dividing the main clock. The following equation is used to obtain the baud rate from the main clock.
Page 325 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-42. Error Tolerance (When k = 16), Including Sampling Errors Ideal sampling point 256T 288T 320T 352T 304T 336T Basic timing START STOP (clock cycle T) 15.5T High-speed clock (clock cycle T’) START STOP enabling normal Sampling error reception...
Page 326 CHAPTER 10 SERIAL INTERFACE FUNCTION (3) Communication operations (a) Data format As shown in Figure 10-43, the format of the transmit/receive data consists of a start bit, character bits, a parity bit, and one or more stop bits. Asynchronous serial interface mode register n (ASIMn) is used to set the character bit length, parity selection, and stop bit length within each data frame (n = 0, 1).
Page 327 CHAPTER 10 SERIAL INTERFACE FUNCTION (b) Parity types and operations The parity bit is used to detect bit errors in transfer data. Usually, the same type of parity bit is used by the transmitting and receiving sides. When odd parity or even parity is set, errors in the parity bit (the odd- number bit) can be detected.
Page 328 CHAPTER 10 SERIAL INTERFACE FUNCTION (c) Transmission The transmit operation is started when transmit data is written to transmit shift register n (TXSn). A start bit, parity bit, and stop bit(s) are automatically added to the data. Starting the transmit operation shifts out the data in TXSn, thereby emptying TXSn, after which a transmit completion interrupt (INTSTn) is issued.
Page 329 CHAPTER 10 SERIAL INTERFACE FUNCTION (d) Reception The receive operation is enabled when “1” is set to bit 6 (RXEn) of asynchronous serial interface mode register n (ASIMn), and input via the RXDn pin is sampled. The serial clock specified by ASIMn is used when sampling the RXDn pin. When the RXDn pin goes low, the 8-bit counter begins counting and the start timing signal for data sampling is output when half of the specified baud rate time has elapsed.
Page 330 CHAPTER 10 SERIAL INTERFACE FUNCTION (e) Receive error There are three types of errors during a receive operation: a pariy error, framing error, and overrun error. When, as the result of data receive, an error flag is set in asynchronous serial interface status register n (ASISn), the receive error interrupt request (INTSERn) is generated.
Page 331 CHAPTER 10 SERIAL INTERFACE FUNCTION 10.4.4 Standby function (1) Operation in HALT mode Serial transfer operations are performed normally. (2) Operation in STOP and IDLE modes (a) When internal clock is selected as serial clock The operations of asynchronous serial interface mode register n (ASIMn), transmit shift register n (TXSn), and receive buffer register n (RXBn) are stopped and their values immediately before the clock stopped are hold.
Page 332 CHAPTER 10 SERIAL INTERFACE FUNCTION 10.5 3-Wire Variable-Length Serial I/O (CSI4) CSI4 has the following two operation modes. (1) Operation stop mode This mode is used when serial transfers are not performed. (2) 3-wire variable-length serial I/O mode (MSB/LSB first switchable) This mode transfers variable data of 8 to 16 bits via three lines: serial clock (SCK4), serial output (SO4), and serial input (SI4).
Page 333 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-47. Block Diagram of CSI4 Internal bus Direction controller Variable-length I/O shift register 4 (8-/16-bit) Serial clock counter Interrupt INTCSI4 (8-/16-bit switchable) generator Baud rate Serial clock controller Selector generator SCK4 (1) Variable-length serial I/O shift register 4 (SIO4) SIO4 is a 16-bit variable register that performs parallel-serial conversion and transmit/receive (shift operations) synchronized with the serial clock.
Page 334 CHAPTER 10 SERIAL INTERFACE FUNCTION When the transfer bit length is set to other than 16 bits and data is set to the shift register, data should be aligned from the lowest bit of the shift register, regardless of whether MSB or LSB is set for the first transfer bit. Any data can be set to the unused higher bits, however, in this case the received data after a serial transfer operation becomes 0.
Page 335 CHAPTER 10 SERIAL INTERFACE FUNCTION 10.5.2 CSI4 control registers CSI4 uses the following type of registers for control functions. • Variable-length serial control register 4 (CSIM4) • Variable-length serial setting register 4 (CSIB4) • Baud rate generator source clock selection register 4 (BRGCN4) •...
Page 336 CHAPTER 10 SERIAL INTERFACE FUNCTION (2) Variable-length serial setting register 4 (CSIB4) CSIB4 is used to set the operation format of the serial interface channel 4. The bit length of a variable register is set by setting bits 3 to 0 (BSEL3 to BSEL0) of variable-length serial setting register 4.
Page 337 CHAPTER 10 SERIAL INTERFACE FUNCTION (3) Baud rate generator source clock selection register 4 (BRGCN4) BRGCN4 can be set by an 8-bit memory manipulation instruction. RESET input clears BRGCN4 to 00H. Figure 10-52. Baud Rate Generator Source Clock Selection Register 4 (BRGCN4) After reset: 00H Address: FFFFF2E6H BRGCN4...
Page 338 CHAPTER 10 SERIAL INTERFACE FUNCTION (4) Baud rate generator output clock selection register 4 (BRGCK4) BRGCK4 is set by an 8-bit memory manipulation instruction. RESET input sets BRGCK4 to 7FH. Figure 10-53. Baud Rate Generator Output Clock Selection Register 4 (BRGCK4) After reset: 7FH Address: FFFFF2E8H BRGCK4...
Page 339 CHAPTER 10 SERIAL INTERFACE FUNCTION 10.5.3 Operations CSI4 has the following two operation modes. • Operation stop mode • 3-wire variable-length serial I/O mode (1) Operation stop mode In this mode serial transfers are not performed and therefore power consumption can be reduced. When in operation stop mode, SI4, SO4, and SCK4 can be used as normal I/O ports.
Page 340 CHAPTER 10 SERIAL INTERFACE FUNCTION (2) 3-wire variable-length serial I/O mode The 3-wire variable-length serial I/O mode is useful when connecting to a peripheral I/O device that includes a clocked serial interface, a display controller, etc. This mode executes data transfers via three lines: a serial clock line (SCK4), serial output line (SO4), and serial input line (SI4).
Page 341 CHAPTER 10 SERIAL INTERFACE FUNCTION The bit length of a variable-length register is set by setting bits 3 to 0 (BSEL3 to BSEL0) of CSIB4. Data is transferred MSB first while bit 4 (DIR) is 1, and is transferred LSB first while DIR is 0. Figure 10-56.
Page 342 CHAPTER 10 SERIAL INTERFACE FUNCTION (b) Communication Operations In the 3-wire variable-length serial I/O mode, data is transmitted and received in 8 to 16-bit units, and is specified by setting bits 3 to 0 (BSEL3 to BSEL0) of variable-length serial setting register 4 (CSIB4). Each bit of data is transmitted or received in synchronization with the serial clock.
Page 343 CHAPTER 10 SERIAL INTERFACE FUNCTION (c) Transfer start A serial transfer becomes possible when the following two conditions have been satisfied. • The SIO4 operation control bit (CSIE4) = 1 • After a serial transfer, the internal serial clock is stopped. Serial transfer starts when the following operation is performed after the above two conditions have been satisfied.
Page 344 CHAPTER 11 A/D CONVERTER 11.1 Function The A/D converter converts analog input signals into digital values with a resolution of 10 bits, and can handle 12 channels of analog input signals (ANI0 to ANI11). The V850/SB1 and V850/SB2 support the low power consumption mode by low-speed conversion. (1) Hardware start Conversion is started by trigger input (ADTRG) (rising edge, falling edge, or both rising and falling edges can be specified).
Page 345 CHAPTER 11 A/D CONVERTER The block diagram is shown below. Figure 11-1. Block Diagram of A/D Converter ANI0 ANI1 ANI2 Sample & hold circuit ANI3 ANI4 Voltage comparator ANI5 ANI6 ANI7 ANI8 ANI9 ANI10 Successive ANI11 approximation register (SAR) Edge ADTRG Controller INTAD...
Page 346 CHAPTER 11 A/D CONVERTER 11.2 Configuration The A/D converter includes the following hardware. Table 11-1. Configuration of A/D Converter Item Configuration Analog input 12 channels (ANI0 to ANI11) Registers Successive approximation register (SAR) A/D conversion result register (ADCR) A/D conversion result register H (ADCRH): Only higher 8 bits can be read Control registers A/D converter mode register 1 (ADM1)
Page 347 CHAPTER 11 A/D CONVERTER (6) ANI0 to ANI11 pins These are analog input pins for the 12 channels of the A/D converter, and are used to input the analog signals to be converted into digital signals. Pins other than ones selected as analog input with the analog input channel specification register (ADS) can be used as input ports.
Page 348 CHAPTER 11 A/D CONVERTER 11.3 Control Registers The A/D converter is controlled by the following registers. A/D converter mode register 1 (ADM1) • Analog input channel specification register (ADS) • A/D converter mode register 2 (ADM2) • (1) A/D converter mode register 1 (ADM1) This register specifies the conversion time of the input analog signal to be converted into a digital signal, starting or stopping the conversion, and an external trigger.
Page 349 CHAPTER 11 A/D CONVERTER Figure 11-2. A/D Converter Mode Register 1 (ADM1) (2/2) After reset: Address: FFFFF3C0H <7> <6> <0> ADM1 ADCS EGA1 EGA0 ADPS ADPS Selection of conversion time Note 1 Conversion time Note 2 + stabilization time Note 3 20 MHz 12.58 MHz 8.4 µ...
Page 350 CHAPTER 11 A/D CONVERTER (2) Analog input channel specification register (ADS) ADS specifies the port for inputting an analog voltage to be converted into a digital signal. ADS is set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears ADS to 00H. Figure 11-3.
Page 351 CHAPTER 11 A/D CONVERTER 11.4 Operation 11.4.1 Basic operation <1> Select one channel whose analog signal is to be converted into a digital signal by using the analog input channel specification register (ADS). <2> The sample & hold circuit samples the voltage input to the selected analog input channel. <3>...
Page 352 CHAPTER 11 A/D CONVERTER Figure 11-5. Basic Operation of A/D Converter Conversion time Sampling time Operation of Sampling A/D conversion A/D converter Conversion Undefined result Conversion ADCR result INTAD A/D conversion is successively executed until bit 7 (ADCS) of A/D converter mode register 1 (ADM1) is reset to 0 by software.
Page 353 CHAPTER 11 A/D CONVERTER 11.4.2 Input voltage and conversion result The analog voltages input to the analog input pins (ANI0 to ANI11) and the result of the A/D conversion (contents of the A/D conversion result register (ADCR)) are related as follows: ×...
Page 354 CHAPTER 11 A/D CONVERTER 11.4.3 A/D converter operation mode In this mode one of the analog input channels ANI0 to ANI11 is selected by the analog input channel specification register (ADS) and A/D conversion is executed. The A/D conversion can be started in the following two ways: Hardware start: Started by trigger input (ADTRG) (rising edge, falling edge, or both rising and falling edges •...
Page 355 CHAPTER 11 A/D CONVERTER (2) A/D conversion by software start If bit 6 (TRG) and bit 7 (ADCS) of A/D converter mode register 1 (ADM1) are set to 1, the A/D converter starts converting the voltage applied to an analog input pin specified by the analog input channel specification register (ADS) into a digital signal.
Page 356 CHAPTER 11 A/D CONVERTER 11.5 Low Power Consumption Mode The V850/SB1 and V850/SB2 feature a function that can cut or connect the current between AV and AV Switching can be performed by setting A/D converter mode register 2 (ADM2). = AV When AV , and when the system does not require high precision, current consumption can be reduced by connecting AV...
Page 357 CHAPTER 11 A/D CONVERTER (4) Countermeasures against noise To keep the resolution of 10 bits, prevent noise from being superimposed on the AV and ANI0 to ANI11 pins. The higher the output impedance of the analog input source, the heavier the influence of noise. To lower noise, connecting an external capacitor as shown in Figure 11-9 is recommended.
Page 358 CHAPTER 11 A/D CONVERTER (7) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the contents of the analog input channel specification register (ADS) are changed. If the analog input pin is changed during conversion, therefore, the result of the A/D conversion of the preceding analog input signal and the conversion end interrupt request flag may be set immediately before ADS is rewritten.
Page 359 CHAPTER 11 A/D CONVERTER (8) AV The AV pin is the power supply pin of the analog circuit, and also supplies power to the input circuit of ANI0 to ANI11. Even in an application where a back-up power supply is used, therefore, be sure to apply the same voltage as the V pin to the AV pin as shown in Figure 11-11.
Page 360 CHAPTER 12 DMA FUNCTIONS 12.1 Functions The DMA (Direct Memory Access) controller transfers data between memory and peripheral I/Os based on DMA requests sent from on-chip peripheral hardware (such as the serial interface, timer, or A/D converter). This product includes six independent DMA channels that can transfer data in 8-bit and 16-bit units. maximum number of transfers is 256 (when transferring data in 8-bit units).
Page 361 CHAPTER 12 DMA FUNCTIONS 12.3.2 DMA internal RAM address registers 0 to 5 (DRA0 to DRA5) These registers set DMA channel n internal RAM addresses (n = 0 to 5). Since each product has a different internal RAM capacity, the internal RAM areas that are usable for DMA differ depending on the product.
Page 362 CHAPTER 12 DMA FUNCTIONS (1) Correspondence between DRAn setting value and internal RAM area (a) V850/SB1 ( µ µ µ µ PD703031A, 703031AY), V850/SB2 ( µ µ µ µ PD703034A, 703034AY) Set the DRAn register to a value in the range of 0000H to 2FFFH (n = 0 to 5). Setting is prohibited for values between 3000H and 3FFFH.
Page 363 CHAPTER 12 DMA FUNCTIONS (b) V850/SB1 ( µ µ µ µ PD703033A, 703033AY, 70F3033A, 70F3033AY) V850/SB2 ( µ µ µ µ PD703035A, 703035AY, 70F3035A, 70F3035AY) Set the DRAn register to a value in the range of 000H to 2FFFH or 3000H to 3FFFH (n = 0 to 5). Figure 12-4.
Page 364 CHAPTER 12 DMA FUNCTIONS (c) V850/SB1 ( µ µ µ µ PD703030A, 703030AY), V850/SB2 ( µ µ µ µ PD703036A, 703036AY) Set the DRAn register to a value in the range of 0000H to 0FFFH or 2000H to 3FFFH (n = 0 to 5). Setting is prohibited for values between 1000H to 1FFFH.
Page 365 CHAPTER 12 DMA FUNCTIONS (d) V850/SB1 ( µ µ µ µ PD703032A, 703032AY, 70F3032A, 70F3032AY) V850/SB2 ( µ µ µ µ PD703037A, 703037AY, 70F3037A, 70F3037AY) Set the DRAn register to a value in the range of 0000H to 0FFFH or 1000H to 3FFFH (n = 0 to 5). Figure 12-6.
Page 366 CHAPTER 12 DMA FUNCTIONS 12.3.3 DMA byte count registers 0 to 5 (DBC0 to DBC5) These are 8-bit registers that are used to set the number of transfers for DMA channel n. The remaining number of transfers is retained during the DMA transfers. A value of 1 is decremented once per transfer if the transfer is a byte (8-bit) transfer, and a value of 2 is decremented once per transfer if the transfer is a 16-bit transfer.
Page 367 CHAPTER 12 DMA FUNCTIONS 12.3.5 DMA channel control registers 0 to 5 (DCHC0 to DCHC5) These registers are used to control the DMA transfer operation mode for DMA channel n. These registers are can be read/written in 1-bit or 8-bit units. Figure 12-9.
Page 368 CHAPTER 12 DMA FUNCTIONS Figure 12-9. Format of DMA Channel Control Registers 0 to 5 (DCHC0 to DCHC5) (2/2) After reset: Address: DCHC0 FFFFF186H DCHC3 FFFFF1B6H DCHC1 FFFFF196H DCHC4 FFFFF1C6H DCHC2 FFFFF1A6H DCHC5 FFFFF1D6H <7> <5> <2> <1> <0> DCHCn DDADn TTYPn1 TTYPn0...
Page 369 CHAPTER 13 REAL-TIME OUTPUT FUNCTION (RTO) 13.1 Function The real-time output function transfers preset data to real-time output buffer registers (RTBL, RTBH), and then transfers this data with hardware to an external device via the output latches, upon the occurrence of an external interrupt or external trigger.
Page 370 CHAPTER 13 REAL-TIME OUTPUT FUNCTION (RTO) 13.2 Configuration RTO includes the following hardware. Table 13-1. Configuration of RTO Item Configuration Registers Real-time output buffer registers (RTBL, RTBH) Control registers Real-time output port mode register (RTPM) Real-time output port control register (RTPC) (1) Real-time output buffer registers (RTBL, RTBH) RTBL and RTBH are 4-bit registers that hold output data in advance.
Page 371 CHAPTER 13 REAL-TIME OUTPUT FUNCTION (RTO) Table 13-2. Operation When Real-Time Output Buffer Registers Are Manipulated Note 1 Note 2 Operation Mode Register to Be Manipulated Read Write Higher 4 bits Lower 4 bits Higher 4 bits Lower 4 bits 4 bits ×...
Page 372 CHAPTER 13 REAL-TIME OUTPUT FUNCTION (RTO) (2) Real-time output port control register (RTPC) This register sets the operation mode and output trigger of the real-time output port. The relationship between the operation mode and output trigger of the real-time output port is as shown in Table 13- RTPC is set by an 8-/1-bit memory manipulation instruction.
Page 373 CHAPTER 13 REAL-TIME OUTPUT FUNCTION (RTO) 13.4 Operation If the real-time output operation is enabled by setting the bit 7 (RTPOE) of the real-time output port control register (RTPC) to 1, the data of the real-time output buffer registers (RTBH and RTBL) is transferred to the output latch in Note synchronization with the generation of the selected transmit trigger (set by EXTR and BYTE ).
Page 374 CHAPTER 13 REAL-TIME OUTPUT FUNCTION (RTO) 13.5 Usage (1) Disable the real-time output operation. Clear bit 7 (RTPOE) of the real-time output port control register (RTPC) to 0. (2) Initialization • Set the initial value to the output latch. • Specify the real-time output port mode or port mode in 1-bit units. Set the real-time output port mode register (RTPM).
Page 375 CHAPTER 14 PORT FUNCTION 14.1 Port Configuration The V850/SB1 and V850/SB2 include 83 I/O port pins from ports 0 to 11 (12 ports are input only). There are three power supplies for the I/O buffers; AV , BV , and EV , which are described below.
Page 376 CHAPTER 14 PORT FUNCTION Port 0 includes the following alternate functions. Table 14-2. Port 0 Alternate Function Pins Note Pin Name Alternate Function PULL Remark Port 0 Analog noise elimination INTP0 INTP1 INTP2 INTP3 INTP4/ADTRG Digital noise elimination INTP5/RTPTRG INTP6 Note Software pull-up function (1) Function of P0 pins Port 0 is an 8-bit I/O port for which I/O settings can be controlled in 1-bit units.
Page 377 CHAPTER 14 PORT FUNCTION Cautions 1. If the input pulse width is 2 or 3 clock, whether it will be detected as a valid edge or eliminated as noise is undermined. 2. To ensure correct detection of pulses as pulses, constant-level input is required for 3 clocks or more.
Page 378 CHAPTER 14 PORT FUNCTION (c) Rising edge specification register 0 (EGP0) EGP0 can be read/written in 8-/1-bit units. Figure 14-4. Rising Edge Specification Register 0 (EGP0) After reset: Address: FFFFF0C0H <7> <6> <5> <4> <3> <2> <1> <0> EGP0 EGP07 EGP06 EGP05 EGP04...
Page 379 CHAPTER 14 PORT FUNCTION (4) Block diagram (Port 0) Figure 14-6. Block Diagram of P00 to P07 P-ch PU0n Selector P00/NMI P01/INTP0 PORT P02/INTP1 Output latch P03/INTP2 (P0n) P04/INTP3 P05/INTP4/ADTRG P06/INTP5/RTPTRG P07/INTP6 PM0n Remarks 1. PU0: Pull-up resistor option register 0 PM0: Port 0 mode register Port 0 read signal Port 0 write signal...
Page 380 CHAPTER 14 PORT FUNCTION 14.2.2 Port 1 Port 1 is a 6-bit I/O port for which I/O settings can be controlled in 1-bit units. A pull-up resistor can be connected in 1-bit units (software pull-up function). Bits 0, 1, 2, 4, and 5 are selectable as normal outputs or N-ch open-drain outputs. Figure 14-7.
Page 381 CHAPTER 14 PORT FUNCTION (1) Function of P1 pins Port 1 is a 6-bit I/O port for which I/O settings can be controlled in 1-bit units. I/O settings are controlled via the port 1 mode register (PM1). In output mode, the values set to each bit are output to the port 1 register (P1). The port 1 function register (PF1) can be used to specify whether P10 to P12, P14, and P15 are normal outputs or N-ch open-drain outputs.
Page 382 CHAPTER 14 PORT FUNCTION (c) Port 1 function register (PF1) PF1 can be read/written in 8-/1-bit units. Figure 14-10. Port 1 Function Register (PF1) After reset: Address: FFFFF0A2H Note PF15 PF14 PF12 PF11 PF10 PF1n Control of normal output/N-ch open-drain output (n = 0 to 2, 4, 5) Normal output N-ch open-drain output Note Bit 3 is fixed as a normal output.
Page 383 CHAPTER 14 PORT FUNCTION Figure 14-12. Block Diagram of P13 PU13 P-ch Selector PORT Output latch (P13) P13/SI1/RxD0 PM13 Alternate function Remark PU1: Pull-up resistor option register 1 PM1: Port 1 mode register Port 1 read signal Port 1 write signal User’s Manual U13850EJ4V0UM...
Page 384 CHAPTER 14 PORT FUNCTION 14.2.3 Port 2 Port 2 is an 8-bit I/O port for which I/O settings can be controlled in 1-bit units. A pull-up resistor can be connected in 1-bit units (software pull-up function). P20, P21, P22, P24 and P25 are selectable as normal outputs or N-ch open-drain outputs. When P26 and P27 are used as TI2 and TI3 pins, noise is eliminated from these pins by a digital noise eliminator.
Page 385 CHAPTER 14 PORT FUNCTION (1) Function of P2 pins Port 2 is an 8-bit I/O port for which I/O settings can be controlled in 1-bit units. I/O settings are controlled via the port 2 mode register (PM2). In output mode, the values set to each bit are output to the port 2 register (P2). The port 2 function register (PF2) can be used to specify whether P20, P21, P22, P24 and P25 are normal outputs or N-ch open-drain outputs.
Page 386 CHAPTER 14 PORT FUNCTION (b) Pull-up resistor option register 2 (PU2) PU2 can be read/written in 8-/1-bit units. Figure 14-15. Pull-Up Resistor Option Register 2 (PU2) After reset: Address: FFFFF084H PU27 PU26 PU25 PU24 PU23 PU22 PU21 PU20 PU2n Control of on-chip pull-up resistor connection (n = 0 to 7) Do not connect Connect (c) Port 2 function register (PF2)
Page 387 CHAPTER 14 PORT FUNCTION (3) Block diagram (Port 2) Figure 14-17. Block Diagram of P20 to P22, P24, and P25 P-ch PU2n Selector PF2n PORT Note P20/SI2/SDA1 Output latch P-ch P21/SO2 (P2n) P22/SCK2/SCL1 Note P24/SO3/TxD1 N-ch P25/SCK3/ASCK1 PM2n Alternate function The SDA1, SCL1 pins apply only to the µ...
Page 388 CHAPTER 14 PORT FUNCTION Figure 14-18. Block Diagram of P23, P26, and P27 PU13 P-ch Selector PORT Output latch (P13) P13/SI1/RxD0 PM13 Alternate function Remarks 1. PU2: Pull-up resistor option register 2 PM2: Port 2 mode register Port 2 read signal Port 2 write signal 2.
Page 389 CHAPTER 14 PORT FUNCTION 14.2.4 Port 3 Port 3 is an 8-bit I/O port for which I/O settings can be controlled in 1-bit units. A pull-up resistor can be connected in 1-bit units (software pull-up function). Either a normal output or N-ch open-drain out can be selected for P33 and P34. When using P36 and P37 as the TI4 and TI5 pins, noise is eliminated by the digital noise eliminator.
Page 390 CHAPTER 14 PORT FUNCTION (1) Function of P3 pins Port 3 is an 8-bit I/O port for which I/O settings can be controlled in 1-bit units. I/O settings are controlled via the port 3 mode register (PM3). In output mode, the values set to each bit are output to the port 3 register (P3). The port 3 function register (PF3) can be used to specify whether P33 and P34 are normal outputs or N-ch open-drain outputs.
Page 391 CHAPTER 14 PORT FUNCTION (c) Port 3 function register (PF3) PF3 can be read/written in 8-/1-bit units. Figure 14-22. Port 3 Function Register (PF3) After reset: Address: FFFFF0A6H PF34 PF33 PF3n Control of normal output/N-ch open-drain output (n = 3, 4) Normal output N-ch open-drain output (3) Block diagram (Port 3)
Page 392 CHAPTER 14 PORT FUNCTION Figure 14-24. Block Diagram of P33 and P34 PU3n P-ch Selector PF3n PORT Output latch P-ch (P3n) P33/TI11/SO4 P34/TO0/A13/SCK4 N-ch PM3n Alternate function Remarks 1. PU3: Pull-up resistor option register 3 RF3: Port 3 function register PM3: Port 3 mode register Port 3 read signal Port 3 write signal...
Page 393 CHAPTER 14 PORT FUNCTION 14.2.5 Ports 4 and 5 Ports 4 and 5 are 8-bit I/O ports for which I/O settings can be controlled in 1-bit units. Figure 14-25. Ports 4 and 5 (P4 and P5) After reset: Address: FFFFF008H, FFFFF00AH Control of output data (in output mode) (n = 4, 5, x = 0 to 7) Outputs 0 Outputs 1...
Page 394 CHAPTER 14 PORT FUNCTION (1) Functions of P4 and P5 pins Ports 4 and 5 are 8-bit I/O ports for which I/O settings can be controlled in 1-bit units. I/O settings are controlled via the port 4 mode register (PM4) the and port 5 mode register (PM5). In output mode, the values set to each bit are output to the port 4 and 5 registers (P4 and P5).
Page 395 CHAPTER 14 PORT FUNCTION (3) Block diagram (Ports 4 and 5) Figure 14-27. Block Diagram of P40 to P47 and P50 to P57 Selector PORT Output latch Pmn/ADx (mn) PMmn Remarks 1. PMm: Port m mode register Port m read signal Port m write signal 2.
Page 396 CHAPTER 14 PORT FUNCTION 14.2.6 Port 6 Port 6 is a 6-bit I/O port for which I/O settings can be controlled in 1-bit units. Figure 14-28. Port 6 (P6) After reset: Address: FFFFF00CH Control of output data (in output mode) (n = 0 to 5) Outputs 0 Outputs 1 Remark...
Page 397 CHAPTER 14 PORT FUNCTION (1) Function of P6 pins Port 6 is a 6-bit I/O port for which I/O settings can be controlled in 1-bit units. I/O settings are controlled via the port 6 mode register (PM6). In output mode, the values set to each bit are output to the port 6 register (P6). When using this port in input mode, the pin statuses can be read by reading the P6 register.
Page 398 CHAPTER 14 PORT FUNCTION (3) Block diagram (Port 6) Figure 14-30. Block Diagram P60 to P65 Selector PORT Output latch P6n/Ax (P6n) PM6n Remarks 1. PM6: Port 6 mode register Port 6 read signal Port 6 write signal 2. n = 0 to 5 x = 16 to 21 User’s Manual U13850EJ4V0UM...
Page 399 CHAPTER 14 PORT FUNCTION 14.2.7 Ports 7 and 8 Port 7 is an 8-bit input port and port 8 is a 4-bit input port. Both ports are read-only and are accessible in 8-/1-bit units. Figure 14-31. Ports 7 and 8 (P7 and P8) After reset: Undefined Address: FFFFF00EH...
Page 400 CHAPTER 14 PORT FUNCTION (1) Functions of P7 and P8 pins Port 7 is an 8-bit input-only port and port 8 is a 4-bit input-only port. The pin statuses can be read by reading the port 7 and 8 registers (P7 and P8). Data cannot be written to P7 or A software pull-up function is not implemented.
Page 401 CHAPTER 14 PORT FUNCTION 14.2.8 Port 9 Port 9 is a 7-bit I/O port for which I/O settings can be controlled in 1-bit units. Figure 14-33. Port 9 (P9) After reset: Address: FFFFF012H Control of output data (in output mode) (n = 0 to 6) Outputs 0 Outputs 1 Remark...
Page 402 CHAPTER 14 PORT FUNCTION (1) Function of P9 pins Port 9 is a 7-bit I/O port for which I/O settings can be controlled in 1-bit units. I/O settings are controlled via the port 9 mode register (PM9). In output mode, the values set to each bit are output to the port 9 register (P9). When using this port in input mode, the pin statuses can be read by reading the P9 register.
Page 403 CHAPTER 14 PORT FUNCTION (3) Block diagram (Port 9) Figure 14-35. Block Diagram of P90 to P96 Selector P90/LBEN/WRL PORT P91/UBEN P92/R/W/WRH Output latch P93/DSTB/RD (P9n) P94/ASTB P95/HLDAK P96/HLDRQ PM9n Remarks 1. PM9: Port 9 mode register Port 9 read signal Port 9 write signal 2.
Page 404 CHAPTER 14 PORT FUNCTION 14.2.9 Port 10 Port 10 is an 8-bit I/O port for which I/O settings can be controlled in 1-bit units. A pull-up resistor can be connected in 1-bit units (software pull-up function). The pins in this port are selectable as normal outputs or N-ch open-drain outputs. When using P100 to P107 as KR0 to KR7 pins, noise is eliminated by the analog noise eliminator.
Page 405 CHAPTER 14 PORT FUNCTION (1) Function of P10 pins Port 10 is an 8-bit I/O port for which I/O settings can be controlled in 1-bit units. I/O settings are controlled via the port 10 mode register (PM10). In output mode, the values set to each bit are output to the port 10 register (P10). The port 10 function register (PF10) can be used to specify whether outputs are normal outputs or N-ch open-drain outputs.
Page 406 CHAPTER 14 PORT FUNCTION (b) Pull-up resistor option register 10 (PU10) PU10 can be read/written in 8-/1-bit units. Figure 14-38. Pull-Up Resistor Option Register 10 (PU10) After reset: Address: FFFFF094H PU10 PU107 PU106 PU105 PU104 PU103 PU102 PU101 PU100 PU10n Control of on-chip pull-up resistor connection (n = 0 to 7) Do not connect Connect...
Page 407 CHAPTER 14 PORT FUNCTION (3) Block diagram (Port 10) Figure 14-40. Block Diagram of P100 to P107 PU10 P-ch PU10n Selector PF10 PF10n P100/RTP0/A5/KR0 PORT P101/RTP1/A6/KR1 Output latch P102/RTP2/A7/KR2 P-ch (P10n) P103/RTP3/A8/KR3 Note P104/RTP4/A9/KR4/IERX PM10 N-ch Note P105/RTP5/A10/KR5/IETX P106/RTP6/A11/KR6 PM10n P107/RTP7/A12/KR7 Alternate function Note...
Page 408 CHAPTER 14 PORT FUNCTION 14.2.10 Port 11 Port 11 is a 4-bit port. A pull-up resistor can be connected to bits 0 to 3 in 1-bit units (software pull-up function). P11 can be read/written in 8-/1-bit units. The on/off of wait function can be switched with a port alternate-function control register (PAC). Caution When using the wait function, set BC to the same potential as EV...
Page 409 CHAPTER 14 PORT FUNCTION (1) Function of P11 pins Port 11 is a 4-bit (total) port for which I/O settings can be controlled in 1-bit units. In output mode, the values set to each bit (bit 0 to bit 3) are output to the port register (P11). When using this port in input mode, the pin statuses can be read by reading the P11 register.
Page 410 CHAPTER 14 PORT FUNCTION (b) Pull-up resistor option register 11 (PU11) PU11 can be read/written in 8-/1-bit units. Figure 14-43. Pull-Up Resistor Option Register 11 (PU11) After reset: Address: FFFFF096H PU11 PU113 PU112 PU111 PU110 PU11n Control of on-chip pull-up resistor connection (n = 0 to 3) Do not connect Connect (c) Port alternate-function control register (PAC)
Page 411 CHAPTER 14 PORT FUNCTION (3) Block diagram (Port 11) Figure 14-45. Block Diagram of P110 to P113 PU11 PU11n P-ch Selector PORT P110/A1/WAIT P111/A2 Output latch P112/A3 (P11n) P113/A4 PM11 PM11n Remarks 1. PU11: Pull-up resistor option register 11 PM11: Port 11 mode register Port 11 read signal Port 11 write signal 2.
Page 412 CHAPTER 14 PORT FUNCTION 14.3 Setting When Port Pin Is Used for Alternate Function When a port pin is used for an alternate function, set the port n mode register (PM0 to PM6 and PM9 to PM11) and output latch as shown in Table 14-12 below. Table 14-12.
Page 413 CHAPTER 14 PORT FUNCTION Table 14-12. Setting When Port Pin Is Used for Alternate Function (2/4) PMnx Bit of Pnx Bit of Other Bits Pin Name Alternate Function PMn Register Pn Register (Register) Function Name  Input PM20 = 1 Setting not needed for P20 Note...
Page 414 CHAPTER 14 PORT FUNCTION Table 14-12. Setting When Port Pin Is Used for Alternate Function (3/4) PMnx Bit of Pnx Bit of Other Bits Pin Name Alternate Function PMn Register Pn Register (Register) Function Name  Output PM35 = 0 P35 = 0 Refer to Figure 3-22 Output...
Page 415 CHAPTER 14 PORT FUNCTION Table 14-12. Setting When Port Pin Is Used for Alternate Function (4/4) PMnx Bit of Pnx Bit of Other Bits Pin Name Alternate Function PMn Register Pn Register (Register) Function Name P100 to P103 RTP0 to RTP3 Output PM100 to PM103 = 0 P100 to P103 = 0...
Page 416 CHAPTER 15 RESET FUNCTION 15.1 General When a low-level input occurs at the RESET pin, a system reset is performed and the various on-chip hardware devices are reset to their initial settings. In addition, oscillation of the main clock is stopped during the reset period, although oscillation of the sub clock continues.
Page 417 CHAPTER 16 REGULATOR 16.1 Outline The V850/SB1 and V850/SB2 incorporate a regulator to realize a 5 V single power supply, low power consumption, and to reduce noise. This regulator supplies a voltage obtained by stepping down V power supply voltage to oscillation blocks and on-chip logic circuits (excluding the A/D converter and output buffers).
Page 418 CHAPTER 17 ROM CORRECTION FUNCTION 17.1 General The ROM correction function provided in the V850/SB1 and V850/SB2 is a function that replaces part of a program in the mask ROM with a program in the internal RAM. First, the instruction of the address where the program replacement should start is replaced with the JMP r0 instruction and the program is instructed to jump to 00000000H.
Page 419 CHAPTER 17 ROM CORRECTION FUNCTION 17.2 ROM Correction Peripheral I/O Registers 17.2.1 Correction control register (CORCN) CORCN controls whether or not the instruction of the correction address is replaced with the JMP r0 instruction when the correction address matches the fetch address (n = 0 to 3). Whether match detection by a comparator is enabled or disabled can be set for each channel.
Page 420 CHAPTER 17 ROM CORRECTION FUNCTION 17.2.2 Correction request register (CORRQ) CORRQ saves the channel in which ROM correction occurred. The JMP r0 instruction makes the program jump to 00000000H after the correction address matches the fetch address. At this time, the program can judge the following cases by reading CORRQ.
Page 421 CHAPTER 17 ROM CORRECTION FUNCTION 17.2.3 Correction address registers 0 to 3 (CORAD0 to CORAD3) CORADn sets the start address of an instruction to be corrected (correction address) in the ROM. Up to four points of the program can be corrected at once since the V850/SB1 and V850/SB2 have four correction address registers (CORADn) (n = 0 to 3).
Page 422 CHAPTER 17 ROM CORRECTION FUNCTION Figure 17-5. ROM Correction Operation and Program Flow START (reset vector) CORRQn = 0? Microcontroller initialization Clears CORRQn flag. JMP channel n correct code address The address of the internal RAM that Data for ROM correction setting is loaded stores the correction code of channel n from an external memory into the internal should be preset before the instruction...
Page 423 CHAPTER 18 FLASH MEMORY The following products are the flash memory versions of the V850/SB1 and V850/SB2. Caution The flash memory version and mask ROM version differ in noise immunity and noise radiation. If replacing a flash memory version with a mask ROM version when changing from of experimental production to mass production, make a thorough evaluation by using the CS model (not ES model) of the mask ROM version.
Page 424 CHAPTER 18 FLASH MEMORY (b) Area erase Erasure can be performed in area units (there are two 128 KB unit areas). The erasing time is 2.0 s for each area. Area 0: The area of xx000000H to xx01FFFFH (128 KB) is erased Area 1: The area of xx020000H to xx03FFFFH (128 KB) is erased (2) V850/SB1 ( µ...
Page 425 CHAPTER 18 FLASH MEMORY 18.3 Programming Environment The following shows the environment required for writing programs to the flash memory of the V850/SB1 and V850/SB2. Figure 18-1. Environment Required for Writing Programs to Flash Memory RS-232C RESET UART/CSI V850/SB1, Dedicated flash programmer V850/SB2 Host machine A host machine is required for controlling the dedicated flash programmer.
Page 426 CHAPTER 18 FLASH MEMORY (2) CSI0 Serial clock: Up to 1 MHz (MSB first) Figure 18-3. Communication with Dedicated Flash Programmer (CSI0) RESET RESET V850/SB1, Dedicated flash V850/SB2 programmer SCK0 (3) CSI0 + + + + HS Serial clock: Up to 1 MHz (MSB first) Figure 18-4.
Page 427 CHAPTER 18 FLASH MEMORY Table 18-1. Signal Generation of Dedicated Flash Programmer (PG-FP3) PG-FP3 V850/SB1, Connection Handling V850/SB2 CSI0 + HS Signal Name Pin Function Pin Name CSI0 UART0 Output Writing voltage voltage generation/ voltage monitoring − Ground Note × ×...
Page 428 CHAPTER 18 FLASH MEMORY 18.5 Pin Connection When performing on-board writing, install a connector on the target system to connect to the dedicated flash programmer. Also, install a function on-board to switch from the normal operation mode to the flash memory programming mode.
Page 429 CHAPTER 18 FLASH MEMORY (1) Conflict of signals When connecting a dedicated flash programmer (output) to a serial interface pin (input) that is connected to another device (output), conflict of signals occurs. To avoid the conflict of signals, isolate the connection to the other device or set the other device to the output high-impedance status.
Page 430 CHAPTER 18 FLASH MEMORY (2) Malfunction of other device When connecting a dedicated flash programmer (output or input) to a serial interface pin (input or output) that is connected to another device (input), the signal output to the other device may cause the device to malfunction. To avoid this, isolate the connection to the other device or make the setting so that the input signal to the other device is ignored.
Page 431 CHAPTER 18 FLASH MEMORY 18.5.3 RESET pin When connecting the reset signals of the dedicated flash programmer to the RESET pin that is connected to the reset signal generator on-board, conflict of signals occurs. To avoid the conflict of signals, isolate the connection to the reset signal generator.
Page 432 CHAPTER 18 FLASH MEMORY 18.6 Programming Method 18.6.1 Flash memory control The following shows the procedure for manipulating the flash memory. Figure 18-9. Procedure for Manipulating Flash Memory Start Supplies RESET pulse Switch to flash memory programming mode Select communication system Manipulate flash memory End? User’s Manual U13850EJ4V0UM...
Page 433 CHAPTER 18 FLASH MEMORY 18.6.2 Flash memory programming mode When rewriting the contents of flash memory using the dedicated flash programmer, set the V850/SB1 or V850/SB2 in the flash memory programming mode. When switching modes, set the V pin before releasing reset. When performing on-board writing, change modes using a jumper, etc.
Page 434 CHAPTER 18 FLASH MEMORY 18.6.3 Selection of communication mode In the V850/SB1 and V850/SB2, the communication mode is selected by inputting pulses (16 pulses max.) to the pin after switching to the flash memory programming mode. The V pulse is generated by the dedicated flash programmer.
Page 435 CHAPTER 18 FLASH MEMORY The following shows the commands for flash memory control of the V850/SB1 and V850/SB2. All of these commands are issued from the dedicated flash programmer, and the V850/SB1 and V850/SB2 perform the various processing corresponding to the commands. Table 18-4.
Page 436 CHAPTER 19 IEBus CONTROLLER (V850/SB2) IEBus (Inter Equipment Bus) is a small-scale digital data transfer system that transfers data between units. To implement IEBus with the V850/SB2, an external IEBus driver and receiver are necessary because they are not provided. The internal IEBus controller of the V850/SB2 is of negative logic.
Page 437 CHAPTER 19 IEBus CONTROLLER (V850/SB2) (6) Communication scale The communication scale of IEBus is as follows: • Number of units: 50 MAX. • Cable length: 150 m MAX. (when twisted pair cable is used) Caution The communication scale in an actual system differs depending on the characteristics of the cables, etc., constituting the IEBus driver/receiver and IEBus.
Page 438 CHAPTER 19 IEBus CONTROLLER (V850/SB2) 19.1.4 Communication address With the IEBus, each unit is assigned a specific 12-bit address. This communication address consists of the following identification numbers: • Higher 4 bits: Group number (number to identify the group to which each unit belongs) •...
Page 439 CHAPTER 19 IEBus CONTROLLER (V850/SB2) 19.1.6 Transfer format of IEBus Figure 19-1 shows the transfer signal format of the IEBus. Figure 19-1. IEBus Transfer Signal Format Master Slave Telegraph Header address address Control field length Data field field field field Tele- Broad- Master...
Page 440 CHAPTER 19 IEBus CONTROLLER (V850/SB2) (3) Master address field The master address field is output by the master to inform a slave of the master’s address. The configuration of the master address field is as shown in Figure 19-2. If two or more units start transmitting the broadcasting bit at the same time, the master address field makes a judgment of arbitration.
Page 441 CHAPTER 19 IEBus CONTROLLER (V850/SB2) (4) Slave address field The master outputs the address of the unit with which it is to communicate. Figure 19-3 shows the configuration of the slave address field. A parity bit is output after a 12-bit slave address has been transmitted in order to prevent a wrong slave address from being received by mistake.
Page 442 CHAPTER 19 IEBus CONTROLLER (V850/SB2) Table 19-2. Contents of Control Bits Note 1 Bit 3 Bit 2 Bit 1 Bit 0 Function Reads slave status Undefined Undefined Note 2 Reads data and locks Note 3 Reads lock address (lower 8 bits) Note 3 Reads lock address (higher 4 bits) Note 2...
Page 443 CHAPTER 19 IEBus CONTROLLER (V850/SB2) If the control bit received from the master unit is not as shown in Table 19-3, the unit locked by the master unit rejects acknowledging the control bit, and does not output the acknowledge bit. Table 19-3.
Page 444 CHAPTER 19 IEBus CONTROLLER (V850/SB2) Table 19-5. Acknowledge Signal Output Condition of Control Field (a) If received control data is AH, BH, EH, or FH Communication Lock Status Master Unit Slave Slave Reception Received Control Data Target (SLVRQ) (LOCK) Identification Transmission Enable Slave...
Page 445 CHAPTER 19 IEBus CONTROLLER (V850/SB2) (6) Telegraph length field This field is output by the transmission side to inform the reception side of the number of bytes of the transmit data. The configuration of the telegraph length field is as shown in Figure 19-5. Table 19-6 shows the relationship between the telegraph length bit and the number of transmit data.
Page 446 CHAPTER 19 IEBus CONTROLLER (V850/SB2) (7) Data field This is data output by the transmission side. The master unit transmits or receives data to or from a slave unit by using the data field. The configuration of the data field is as shown below. Figure 19-6.
Page 447 CHAPTER 19 IEBus CONTROLLER (V850/SB2) The operation differs as follows depending on whether the master transmits or receives data. (a) When master transmits data When the master units writes data to a slave unit, the master unit transmits the data bit and parity bit to the slave unit.
Page 448 CHAPTER 19 IEBus CONTROLLER (V850/SB2) (9) Acknowledge bit During normal communication (communication from one unit to another), an acknowledge bit is appended to the following locations to check if the data has been correctly received. • End of slave address field •...
Page 449 CHAPTER 19 IEBus CONTROLLER (V850/SB2) (c) Last acknowledge bit of telegraph length field The last acknowledge bit of the telegraph length field serves as NACK in any of the following cases, and transmission is stopped. • If the parity of the telegraph length bit is incorrect •...
Page 450 CHAPTER 19 IEBus CONTROLLER (V850/SB2) Figure 19-7. Bit Configuration of Slave Status Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Note 1 Bit 0 Meaning Transmit data is not written in IEBus data register (DR) Transmit data is written in IEBus data register (DR) Note 2 Bit 1...
Page 451 CHAPTER 19 IEBus CONTROLLER (V850/SB2) (2) Lock address When the lock address is read (control bit: 4H or 5H), the address (12 bits) of the master unit that has issued the lock instruction is configured in 1-byte units as shown below and read. Figure 19-8.
Page 452 CHAPTER 19 IEBus CONTROLLER (V850/SB2) (c) Lock setting conditions Control Data Broadcasting Communication Individual Communication Communication End Frame End Communication End Frame End Note 3H, 6H Cannot be locked Lock set AH, BH Cannot be locked Cannot be locked Cannot be locked Lock set 0H, 4H, 5H, EH, FH Cannot be locked...
Page 453 CHAPTER 19 IEBus CONTROLLER (V850/SB2) 19.2 IEBus Controller Configuration The block diagram of the IEBus controller is shown below. Figure 19-10. IEBus Controller Block Diagram CPU interface block     BCR(8) UAR(12) SAR(12) PAR(12) CDR(8) DLR(8) DR(8) USR(8) ISR(8) SSR(8) SCR(8)
Page 454 CHAPTER 19 IEBus CONTROLLER (V850/SB2) (a) CPU interface block This is a control block that interfaces between the CPU (V850/SB2) and IEBus. (b) Interrupt control block This control block transfers interrupt request signals from IEBus to the CPU. (c) Internal registers These registers set data to the control registers and fields that control IEBus (for the internal registers, refer to 19.3 Internal Registers of IEBus Controller).
Page 455 CHAPTER 19 IEBus CONTROLLER (V850/SB2) 19.3 Internal Registers of IEBus Controller 19.3.1 Internal register list Table 19-7. Internal Registers of IEBus Controller Address Function Register Name Symbol Bit Units for Manipulation After Reset 1 Bit 8 Bits 16 Bits √ √...
Page 456 CHAPTER 19 IEBus CONTROLLER (V850/SB2) 19.3.2 Internal registers The internal registers incorporated in the IEBus controller are described below. (1) IEBus control register (BCR) Figure 19-11. IEBus Control Register (BCR) After reset: 00H RW Address: FFFFF3E0H <7> <6> <5> <4> <3>...
Page 457 CHAPTER 19 IEBus CONTROLLER (V850/SB2) (a) Communication enable flag (ENIEBUS)...Bit 7 <Set/reset conditions> Set: By software Reset: By software Caution Before setting the ENIBUS flag, make the following setting: • Set the interrupt enabled (EI) status and enable the interrupt processing of INTIE2 (IEBMK = 2).
Page 458 CHAPTER 19 IEBus CONTROLLER (V850/SB2) (d) Slave transmission enable flag (ENSLVTX)...Bit 4 <Set/reset conditions> Set: By software Reset: By software Cautions 1. Clear the ENSLVTX flag before setting the MSTRQ flag when making a master request. If a slave transmission request is sent in slave mode when the ENSLVTX flag is unset, NACK in the control field will be returned.
Page 459 CHAPTER 19 IEBus CONTROLLER (V850/SB2) (2) IEBus unit address register (UAR) This register sets the unit address of an IEBus unit. This register must be always set before starting communication. Sets the unit address (12 bits) to bits 11 to 0. Figure 19-12.
Page 460 CHAPTER 19 IEBus CONTROLLER (V850/SB2) (4) IEBus partner address register (PAR) (a) When slave unit The value of the receive data in the master address field (address of the master unit) is written to this register. If a request “4H” to read the lock address (lower 8 bits) is received from the master, the CPU must read the value of this register, and write it to the lower 8 bits IEBus data register (DR).
Page 461 CHAPTER 19 IEBus CONTROLLER (V850/SB2) Figure 19-15. IEBus Control Data Register (CDR) Format After reset: 01H Address: FFFFF3E8H SELCL2 SELCL1 SELCL0 SELCL2 SELCL1 SELCL0 Function Reads slave status Undefined Undefined Reads data and locks Reads lock address (lower 8 bits) Reads lock address (lower 4 bits) Reads slave status and unlocks Reads data...
Page 462 CHAPTER 19 IEBus CONTROLLER (V850/SB2) (c) Slave status return operation When the IEBus receives a request to transfer from master to slave status or a lock address request (control data: 0H, 6H), whether ACK in the control field is returned or not depends on the status of the IEBus unit.
Page 463 CHAPTER 19 IEBus CONTROLLER (V850/SB2) Figure 19-17. Interrupt Generation Timing (for (2) and (5)) Control field IEBus sequence Control bits (4 bits) Parity bit (1 bit) ACK bit (1 bit) Terminated by communication error INTIE2 Flag reset by CPU processing Flag set by reception of 0H, 4H, 5H, 6H STATUSF flag...
Page 464 CHAPTER 19 IEBus CONTROLLER (V850/SB2) Figure 19-19. Timing of INTIE2 Interrupt Generation in Locked State (for (3)) Broad- Start Master address Slave address Control Telegraph length Data IEBus sequence casting (12 + P) (12 + P + A) (4 + P + A) (8 + P + A) (8 + P + A) INTIE2...
Page 465 CHAPTER 19 IEBus CONTROLLER (V850/SB2) Figure 19-20. IEBus Telegraph Length Register (DLR) Format After reset: 01H Address: FFFFF3EAH Setting Remaining number of value communication data bytes 1 byte 2 bytes 32 bytes 255 bytes 256 bytes Cautions 1. If the master issues a request “0H, 4H, 5H, or 6H” to transmit a slave status and lock address (higher 4 bits, lower 8 bits), the contents of this register are set to “01H”...
Page 466 CHAPTER 19 IEBus CONTROLLER (V850/SB2) (7) IEBus data register (DR) The IEBus data register (DR) sets the communication data. Sets the communication data (8 bits) to bits 7 to Remark The IEBus data register consists of a write register and a read register. Consequently, data written to this register cannot be read as is.
Page 467 CHAPTER 19 IEBus CONTROLLER (V850/SB2) (8) IEBus unit status register (USR) Figure 19-22. IEBus Unit Status Register (USR) After reset: 00H Address: FFFFF3EEH <6> <5> <4> <3> <2> SLVRQ ARBIT ALLTRNS LOCK Slave request flag SLVRQ No request from master to slave Request from master to slave Arbitration result flag ARBIT...
Page 468 CHAPTER 19 IEBus CONTROLLER (V850/SB2) (b) Arbitration result flag (ARBIT)...Bit 5 A flag that indicates the result of arbitration. <Set/reset conditions> Set: When the data output by the IEBus unit during the arbitration period does not match the bus line data. Reset: By the start bit timing.
Page 469 CHAPTER 19 IEBus CONTROLLER (V850/SB2) (e) Lock status flag (LOCK)...Bit 2 A flag that indicates whether the unit is locked. <Set/reset conditions> Set: When the communication end flag goes low level and the frame end flag goes high level after receipt of a lock specification (3H, 6H, AH, BH) in the control field.
Page 470 CHAPTER 19 IEBus CONTROLLER (V850/SB2) (9) IEBus interrupt status register (ISR) This register indicates the status when IEBus issues an interrupt. The ISR is read to generate an interrupt, after which the specified interrupt processing is carried out. Reset the ISR register after reading it. Until it is reset, the INTIE2 interrupt signal is not generated (nor held pending).
Page 471 CHAPTER 19 IEBus CONTROLLER (V850/SB2) Figure 19-24. IEBus Interrupt Status Register (ISR) After reset: 00H R/W Address: FFFFF3F0H <6> <5> <4> <3> <2> IEERR STARTF STATUSF ENDTRNS ENDFRAM IEERR Communication error flag (during communication) No communication error Communication error STARTF Start interrupt flag Start interrupt does not occur Start interrupt occurs...
Page 472 CHAPTER 19 IEBus CONTROLLER (V850/SB2) (a) Communication error flag (IEERR)...Bit 6 A flag that indicates the detection of an error during communication. <Set/reset conditions> Set: The flag is set if a timing error, parity error (except in the data field), NACK reception (except in the data field), underrun error, or overrun error (that occurs during broadcasting communication reception) occurs.
Page 473 CHAPTER 19 IEBus CONTROLLER (V850/SB2) (f) Communication error triggers • Timing error Occurrence conditions: Occurs if the high/low level width of the communication bit has shifted from the prescribed value. Remark: The respective prescribed values are set in the bit processing block and monitored by the internal 8-bit timer.
Page 474 CHAPTER 19 IEBus CONTROLLER (V850/SB2) (g) Overrun error - supplementary details (i) When the frame ends in the overrun state during individual communication reception If the DR register is not read after entering the overrun state and the retransmitted data reaches the maximum number of bytes (32 bytes), the frame end interrupt (INTIE2) is generated.
Page 475 CHAPTER 19 IEBus CONTROLLER (V850/SB2) (10)IEBus slave status register (SSR) This register indicates the communication status of the slave unit. After receiving a slave status transmission request from the master, the CPU reads this register, and writes a slave status to the IEBus data register (DR) to transmit the slave status.
Page 476 CHAPTER 19 IEBus CONTROLLER (V850/SB2) (11)IEBus success count register (SCR) The IEBus success count register (SCR) indicates the number of remaining communication bytes. This register reads the count value of the counter that decrements the value set by the telegraph length register by ACK in the data field.
Page 477 CHAPTER 19 IEBus CONTROLLER (V850/SB2) (12)IEBus communication count register (CCR) The IEBus communication count register (CCR) indicates the number of remaining bytes in the communication byte number specified in the communication mode. Bits 7 to 0 of the IEBus communication count register (CCR) indicate the number of transfer bytes. This register reads the count value of the counter that is preset to the maximum number of transmitted bytes (32 bytes) per frame specified in mode 1.
Page 478 CHAPTER 19 IEBus CONTROLLER (V850/SB2) 19.4 Interrupt Operations of IEBus Controller 19.4.1 Interrupt control block Interrupt request signal <1> Communication error IEERR <2> Start interrupt STARTF <3> Status communication STATUSF <4> End of communication ENDTRNS <5> End of frame ENDFRAM <6>...
Page 479 CHAPTER 19 IEBus CONTROLLER (V850/SB2) 19.4.2 Interrupt source list The interrupt request signals of the internal IEBus controller in the V850/SB2 can be classified into vector interrupts and DMA transfer interrupts. These interrupt request signals can be specified through software manipulation. The interrupt sources are listed below.
Page 480 CHAPTER 19 IEBus CONTROLLER (V850/SB2) 19.4.3 Communication error source processing list The following table shows the occurrence conditions of the communication errors (timing error, NACK reception error, overrun error, underrun error, and parity error), error processing by the internal IEBus controller, and examples of processing by software.
Page 481 CHAPTER 19 IEBus CONTROLLER (V850/SB2) Table 19-10. Communication Error Source Processing List (2/2) Overrun Error Underrun Error Occurrence Unit status Reception Transmission condition Occurrence DR cannot be read in time before the next DR cannot be written in time before the next condition data is received.
Page 482 CHAPTER 19 IEBus CONTROLLER (V850/SB2) 19.5 Interrupt Generation Timing and Main CPU Processing 19.5.1 Master transmission Initial preparation processing: Sets a unit address, slave address, control data, telegraph length, and the first byte of the transmit data. Communication start processing: Sets the bus control register (enables communication, master request, and slave reception).
Page 483 CHAPTER 19 IEBus CONTROLLER (V850/SB2) (1) Slave reception processing If a slave reception request is confirmed during vector interrupt processing, the data transfer direction of macro service must change from RAM (memory) ‘ SFR (peripheral) to SFR (peripheral) ‘ RAM (memory) until the first data is received.
Page 484 CHAPTER 19 IEBus CONTROLLER (V850/SB2) 19.5.2 Master reception Before performing master reception, it is necessary to notify the slave of slave transmission units. Therefore, more than two communication frames are necessary for master reception. The slave unit prepares the transmit data, set (1) the slave transmission enable flag (ENSLVTX), and waits. Initial preparation processing: Sets a unit address, slave address, and control data.
Page 485 CHAPTER 19 IEBus CONTROLLER (V850/SB2) (1) Interrupt (INTIE1) occurrence If NACK is transmitted (hardware processing) in the data field, an interrupt (INTIE1) is not issued to the CPU, and the same data is retransmitted from the slave. If the receive data is not read in time until the next data is received, the hardware automatically transmits NACK.
Page 486 CHAPTER 19 IEBus CONTROLLER (V850/SB2) 19.5.3 Slave transmission Initial preparation processing: Sets a unit address, telegraph length, and the first byte of the transmit data. Communication start processing: Sets the bus control register (enables communication, slave transmission, and slave reception). Figure 19-32.
Page 487 CHAPTER 19 IEBus CONTROLLER (V850/SB2) (1) Interrupt (INTIE1) occurrence If NACK is received from the master in the data field, an interrupt (INTIE1) is not issued to the CPU, and the same data is retransmitted by hardware. If the transmit data is not written in time during the period of writing the next data, a communication error interrupt occurs due to occurrence of underrun, and communication is abnormally ended.
Page 488 CHAPTER 19 IEBus CONTROLLER (V850/SB2) 19.5.4 Slave reception Initial preparation processing: Sets a unit address. Communication start processing: Sets the bus control register (enables communication, disables slave transmission, and enables slave reception). Figure 19-33. Slave Reception µ Approx. 1014 s (mode 1) <1>...
Page 489 CHAPTER 19 IEBus CONTROLLER (V850/SB2) (1) Interrupt (INTIE1) occurrence If NACK is transmitted in the data field, an interrupt (INTIE1) is not issued to the CPU, and the same data is retransmitted from the master. If the receive data is not read in time until the next data is received, NACK is automatically transmitted. (2) Frame end processing The vector interrupt processing in <2>...
Page 490 CHAPTER 19 IEBus CONTROLLER (V850/SB2) 19.5.5 Interval of occurrence of interrupt for IEBus control Each control interrupt must occur at each point of communication and perform the necessary processing until the next interrupt occurs. Therefore, the CPU must control the IEBus control block, taking the shortest time of this interrupt into consideration.
Page 491 CHAPTER 19 IEBus CONTROLLER (V850/SB2) (2) Master reception Figure 19-35. Master Reception (Interval of Interrupt Occurrence) Broad- Telegraph Start bit Slave address Control Data Master address casting length Communication starts Communication start interrupt Data Data Data End of communication End of frame Remarks 1.
Page 492 CHAPTER 19 IEBus CONTROLLER (V850/SB2) (3) Slave transmission Figure 19-36. Slave Transmission (Interval of Interrupt Occurrence) Telegraph Broad- Start bit Master address Slave address Control Data casting length Communication starts Communication Status request start interrupt Data Data Data End of communication End of frame Remarks 1.
Page 493 CHAPTER 19 IEBus CONTROLLER (V850/SB2) (4) Slave reception Figure 19-37. Slave Reception (Interval of Interrupt Occurrence) Telegraph Broad- Start bit Master address Slave address Control Data casting length Communication starts Communication start interrupt Data Data Data End of communication End of frame Remarks 1.
Page 494 APPENDIX A REGISTER INDEX (1/7) Symbol Name Unit Page ADCR A/D conversion result register ADCRH A/D conversion result register H ADIC Interrupt control register INTC 139 to 141 ADM1 A/D converter mode register 1 ADM2 A/D converter mode register 2 Analog input channel specification register ASIM0 Asynchronous serial interface mode register 0...
Page 495 APPENDIX A REGISTER INDEX (2/7) Symbol Name Unit Page CR40 8-bit compare register 4 CR45 16-bit compare register 45 (when connected to TM4,TM5 cascade) CR50 8-bit compare register 5 CR60 8-bit compare register 6 CR67 16-bit compare register 67 (when connected to TM6,TM7 cascade) CR70 8-bit compare register 7 CRC0...
Page 496 APPENDIX A REGISTER INDEX (3/7) Symbol Name Unit Page DIOA3 DMA peripheral I/O address register 3 DMAC DIOA4 DMA peripheral I/O address register 4 DMAC DIOA5 DMA peripheral I/O address register 5 DMAC IEBus telegraph length register IEBus DMAIC0 Interrupt control register INTC 139 to 141 DMAIC1...
Page 497 APPENDIX A REGISTER INDEX (4/7) Symbol Name Unit Page IICS0 IIC status register 0 IICS1 IIC status register 1 IICX0 IIC function expansion register 0 IICX1 IIC function expansion register 1 ISPR In-service priority register INTC IEBus interrupt status register IEBus KRIC Interrupt control register...
Page 498 APPENDIX A REGISTER INDEX (5/7) Symbol Name Unit Page Port 0 mode register Port Port 1 mode register Port Port 2 mode register Port Port 3 mode register Port Port 4 mode register Port Port 5 mode register Port Port 6 mode register Port Port 9 mode register Port...
Page 499 APPENDIX A REGISTER INDEX (6/7) Symbol Name Unit Page SIO3 Serial I/O shift register 3 SIO4 Variable length serial I/O shift register 4 IEBus slave status register IEBus STIC0 Interrupt control register INTC 139 to 141 STIC1 Interrupt control register INTC 139 to 141 SVA0...
Page 500 APPENDIX A REGISTER INDEX (7/7) Symbol Name Unit Page TMC6 8-bit timer mode control register 6 TMC7 8-bit timer mode control register 7 TMIC00 Interrupt control register INTC 139 to 141 TMIC01 Interrupt control register INTC 139 to 141 TMIC10 Interrupt control register INTC 139 to 141...
Page 501 APPENDIX B INSTRUCTION SET LIST • How to Read Instruction Set List This column shows instruction groups. Instructions are divided into each instruction group and described. This column shows instruction mnemonics. This column shows instruction operands (refer to Table B-1). This column shows instruction codes (opcode) in binary format.
Page 502 APPENDIX B INSTRUCTION SET LIST Table B-2. Symbols Used for Op Code Symbol Description 1-bit data of code that specifies reg1 or regID 1-bit data of code that specifies reg2 1-bit data of displacement 1-bit data of immediate data cccc 4-bit data that indicates condition code 3-bit data that specifies bit number Table B-3.
Page 503 APPENDIX B INSTRUCTION SET LIST Table B-4. Symbols Used for Flag Operation Symbol Description (blank) Not affected Cleared to 0 × Set of cleared according to result Previously saved value is restored Table B-5. Condition Codes Condition Name (cond) Condition Code (cccc) Conditional Expression Description 0000...
Page 504 APPENDIX B INSTRUCTION SET LIST Instruction Set List (1/4) Mnemonic Operand Op Code Operation Flag Instruction Group CY OV S Z SAT adr ← ep + zero-extend (disp7) Load/store SLD.B disp7 [ep], rrrrr0110ddddddd reg2 GR [reg2] ← sign-extend (Load-memory (adr, Byte)) adr ←...
Page 505 APPENDIX B INSTRUCTION SET LIST Instruction Set List (2/4) Mnemonic Operand Op Code Operation Flag Instruction Group CY OV S Z SAT GR [reg2] ← GR [reg2] + GR [reg1] × × × × Arithmetic reg1, reg2 rrrrr001110RRRRR operation GR [reg2] ← GR [reg2] + sign-extend ×...
Page 506 APPENDIX B INSTRUCTION SET LIST Instruction Set List (3/4) Operand Op Code Mnemonic Operation Flag Instruction Group CY OV S Z SAT GR [reg2] ← GR [reg2] XOR GR [reg1] × × Logic reg1, reg2 rrrrr001001RRRRR operation GR [reg2] ← GR [reg1] XOR zero-extend ×...
Page 507 APPENDIX B INSTRUCTION SET LIST Instruction Set List (4/4) Mnemonic Operand Op Code Operation Flag Instruction Group CY OV S Z SAT SR [regID] ←GR Special LDSR reg2, regID rrrrr111111RRRRR regID = EIPC, FEPC 0000000000100000 [reg2] regID = EIPSW, (Note) FEPSW ×...
Page 508 APPENDIX C INDEX [Number] 16-bit compare register 23 -------------------------------227 ASIM0, ASIM1 ---------------------------------------------- 315 16-bit compare register 45 -------------------------------227 ASIS0, ASIS1 ----------------------------------------------- 316 16-bit compare register 67 -------------------------------227 ASTB ------------------------------------------------------------65 16-bit counter 23 -------------------------------------------227 Asynchronous serial interface -------------------------- 312 16-bit counter 45 -------------------------------------------227 Asynchronous serial interface mode 16-bit counter 67 -------------------------------------------227 registers 0, 1 ------------------------------------------------ 315...
Page 509 APPENDIX C INDEX CDR ----------------------------------------------------------- 460 DSTB ----------------------------------------------------------- 65 CG ----------------------------------------------------------38, 48 DWC ---------------------------------------------------------- 110 CLKOUT --------------------------------------------------------67 Clock generation function -------------------------------- 158 Clock generator (CG) ----------------------------------38, 48 ECR ------------------------------------------------------------- 76 Clock output function ------------------------------------- 160 EGN0 ---------------------------------------------------142, 378 Command register ----------------------------------------- 104 EGP0 ---------------------------------------------------142, 378 Communication command ------------------------------- 434 EIPC ------------------------------------------------------------ 76...
Page 510 APPENDIX C INDEX IEBus control data register ------------------------------460 KR0 to KR7 ----------------------------------------------------66 IEBus control register -------------------------------------456 KRIC -------------------------------------------------139 to 141 IEBus controller ---------------------------------------------436 KRM ----------------------------------------------------------- 156 IEBus data register ----------------------------------------466 IEBus interrupt status register --------------------------470 IEBus partner address register -------------------------460 LBEN ------------------------------------------------------------64 IEBus slave address register ----------------------------460 Low power consumption mode ------------------------- 356...
Page 511 APPENDIX C INDEX P3 -------------------------------------------------------------- 389 Port 2 function register ----------------------------------- 386 P30 to P37 -----------------------------------------------------62 Port 2 mode register -------------------------------------- 385 P4 -------------------------------------------------------------- 393 Port 3 --------------------------------------------------------- 389 P40 to P47 -----------------------------------------------------62 Port 3 function register ----------------------------------- 391 P5 -------------------------------------------------------------- 393 Port 3 mode register -------------------------------------- 390 P50 to P57 -----------------------------------------------------63 Port 4 --------------------------------------------------------- 393...
Page 512 APPENDIX C INDEX RAM ------------------------------------------------------- 38, 48 SI4 ---------------------------------------------------------------62 RD --------------------------------------------------------------- 65 Single-chip mode --------------------------------------------78 Real-time output buffer register H ---------------------370 SIO0 to SIO3 ------------------------------------------------ 245 Real-time output buffer register L ----------------------370 SIO4 ----------------------------------------------------------- 333 Real-time output function --------------------------------369 Slave address registers 0, 1 ---------------------------- 268 Real-time output port control register -----------------372 SO latch ------------------------------------------------------ 255 Real-time output port mode register -------------------371...
Page 513 APPENDIX C INDEX Transfer completion interrupt request ---------------- 360 Watch timer clock selection register ----------------- 233 Transmit shift registers 0, 1 ----------------------------- 313 Watch timer function ------------------------------------- 230 TXD0 ------------------------------------------------------------60 Watch timer mode control register -------------------- 232 TXD1 ------------------------------------------------------------61 Watchdog timer clock selection register ------------ 239 TXS0, TXS1 ------------------------------------------------- 313 Watchdog timer function -------------------------------- 236 Watchdog timer mode ----------------------------------- 237...
Page 514 [MEMO] User’s Manual U13850EJ4V0UM...
Page 515 Facsimile Message Although NEC has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that From: errors may occur. Despite all the care and precautions we’ve taken, you may Name encounter problems in the documentation.

NEC V850/SB1TM User Manual

Chapter 1 Introduction

Chapter 2 Pin Functions

Chapter 3 Cpu Functions

Chapter 4 Bus Control Function

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