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8
7
+5V
R 12
4.7K
U1
EED ATA
1
5
A0
SDA
2
6
A1
SCL
3
7
A2
TEST
D
24C08
(2B3)
EECLK
+5V
R2
R1
R179
4.7K
4.7K
4.7k
+5V
U3
C
DS1233D
1
RESET*
(3C8,5A8,8D6,9C8)
RES
RES ET*
+5V
J1
R5
47K
KYBD/DSP
B
1
RXD1
2
3
TXD1
4
MOTOROLA
BDM PORT
J 7
DS*
BE RR
1
2
BKPT*
3
4
F R EEZE
5
6
RES ET*
B D I N
7
8
A
BDOUT
+5V
9
10
C ONN_BDM
8
7
6
D[0..15]
(2C3)
D 0
T14
109
D 1
T15
110
R174
D 2
T16
111
D 3
T17
112
D 4
T18
75
115
D 5
T19
116
T306
D 6
T20
117
D 7
T21
118
D 8
119
D 9
120
D 10
121
D 11
122
D 12
125
D 13
127
R180
R4
R3
D 14
128
4.7k
4.7K
4.7K
D 15
129
T30
11
BE RR
T31
10
9
7
T313
8
T32
95
T33
98
T34
93
(3B2)
D REQ1*
T35
96
(3B2)
D REQ2*
T314
94
T315
97
T36
12
T37
141
(3C5)
D SACK0*
T38
142
(3C5)
D SACK1*
BDOUT
R 15
47K
T39
24
(3C5)
RXDO
B D I N
25
BKPT*
T40
26
(3C5)
BKPT*
F R EEZE
27
T41
88
(3B1)
DTRCLK
SERD ATA
76
(7B7)
SERDATA
T43
77
81
TXD0
(7B8)
T44
84
T45
85
87
R 10
28
+5V
R 11
4.7K
30
T316
29
4.7K
75
T48
73
(3B1)
TGATE2*
T49
74
31
TOUT2
(3B4)
T310
32
T311
33
T312
34
T305
R175
89
10K
R6
150
+5V
R7
92
10M
X2
3.6864MHz
C 12
C 13
22pF
22pF
6
5
4
D[0..15]
(3D4,5B6,6B7,7D4,8D6,
+5V
U2
68340
140
D0
A0
72
D1
A1
71
D2
A2
70
D3
A3
67
D4
A4
66
D5
A5
65
D6
A6
64
D7
A7
63
D8
A8
62
D9
A9
61
D10
A10
58
D11
A11
57
D12
A12
56
D13
A13
54
D14
A14
53
D15
A15
52
A16
49
HALT
A17
48
BERR
A18
T81
47
A19
T80
46
BR
A20
T79
45
BGACK
A21
T78
44
BG
A22
T77
43
A23
DONE1
T76
130
DONE2
PA0/A24
T75
131
PA1/A25
T74
132
DREQ1
PA2/A26
T73
133
DREQ2
PA3/A27
T72
136
DACK1
PA4/A28
T71
137
DACK2
PA5/A29
138
PA6/A30
OPTO
139
RESET
PA7/A31
22
DSACK0
PB0/MODCK
105
DSACK1
PB3/IRQ3*
101
PB5/IRQ5*
100
IPIPE/BDOUT
PB6/IRQ6*
99
IFETCH/BDIN
PB7/IRQ7*
BKPT/BDCLK
80
FREEZE
RTSA/OP0
86
RTSB/OP1
82
SCLK
OP4
83
OP6
RXD0
108
TXD0
CS0*/AVEC*
107
CTS0
CS1*/IRQ1*/PB1
106
CS2*/IRQ2*/PB2
104
RXD1
CS3*/IRQ4*/PB4
TXD1
5
CTS1
DS
6
AS
TIN1
2
TGATE1
R/W
1
T318
TOUT1
RMC
40
T322
TIN2
FC0
39
T319
TGATE2
FC1
38
T320
TOUT2
FC2
37
T321
FC3
TCK
4
TMS
SIZE0
3
T317
TDI
SIZE1
TDO
C9
0.1uF
19
VCCSYN
X2
16
XFC
14
CLOCK
20
XTAL
R9
X1
10M
18
EXTAL
32.768KHz
C 92
C 15
10pF
22pF
5
4
3
A[0.. 29]
A24
A25
A26
A27
A0
A1
A2
R141
R142
R143
R144
A3
4.7K
4.7K
4.7K
4.7K
A4
A5
A6
A7
A8
A9
A10
A11
+5V
+5V
+5V
A12
A13
A14
C1
C 2
C3
0.1uF
0.1uF
0.1uF
A15
A16
A17
A18
+5V
+5V
+5V
A19
A20
A21
C5
C 6
C7
0.1uF
0.1uF
0.1uF
A22
A23
A24
A25
A26
A27
A28
A29
T70
SPARE1
SPARE1
(3C5)
T69
(7D1)
OPTO
T68
EED ATA
(2D7)
(7D1)
C O LOR
T67
D TR
(3B1)
(7D7)
K Y5
T66
D O NE/PROG*
(3B1,5A8)
T65
T64
F AN
(8D4)
T63
EECLK
(2D7)
T62
T61
D R EQS*
(3B4)
EPLDCT RL
T60
EPLDCTRL
(3C5)
T59
+5V
F L0CS*
(3C8,5C6)
F L1CS*
(3C8,5C3)
T57
SIMM1CS*
(3C8)
T56
R147
SIMM2CS*
(3C8)
10K
T55
DS*
DS*
(3B8)
T54
T53
RW*
(3C8,6A8)
T52
S IZ0
(3C8)
+5V
T186
C 11
C 10
R 14
T50
0.01uF
0.1uF
75
C LOCK
(3C8,5A5)
R 13
R 8
10M
470K
ENCAD, Incorporated
X1
Title
Enhanced Main Board (CPU.sch)
C 14
C 93
Size
Document Number
22pF
10pF
B
205325
Date:
Monday, November 04, 2002
3
2
1
A[0..29]
(3D8,5B6,6D8)
A28
A29
R145
R146
D
4.7K
4.7K
+5V
+5V
C4
C 77
0.1uF
10uF
10V
+5V
C8
0.1uF
C
B
A S*
(3D8)
A
R e v
F
Sheet
2
o f
9
2
1
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