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8
7
Notes:
1.
Circuitry to keep OrCAD from rejecting note sheet
J P1
1
2
3
D
4
5
6
C 84
0.001uF
PO WER
2.
Memory Map
0000 0000 - 00FF FFFF
Flash RAM
(See 204579 for
EPLD-generated select terms.)
0C00 0000 - 0FFF FFFF
Base DRAM
2000 0000 - 3FFF FFFF
Optional SIMM RAM
3.
OrCAD Page Link Statements
|LINK
| cpu.sch
| glue.sch
| dram.sch
| flash.sch
C
| simm.sch
| io.sch
| io2.sch
| stepper.sch
4.
Because the industry standard for 128 megabyte
SIMM's has not assigned a pin to A12, the
current design does not support single bank
128 megabyte SIMM's.
Dual bank 128 megabyte
SIMM's must be used until A12 is defined, A26
and A27 are mux'ed and provided as A12 to the
SIMM, and the EPLD equations modified.
5.
REVISION HISTORY
Initial Release:
ECN No. 84108
A TO B:
ECN No.
84196
B TO C:
ECN No. 84324
Added capacitors C92 to C96 for CISPR22-A compliance.
B
C TO D:
ECN No. 84458
Changed R86 and R87 from 4.7Kohms to 2Kohms.
D TO E:
ECN No. 84457
Changed R17 to R28 from 75 ohms to 33 ohms.
Added test jumpers to flash chip selects for use with EST.
Changed R157 to R172 from 75 ohms to 33 ohms.
Added square test post holes to DRAMOE* and GACS*.
Changed taps on delay line from 10/30 nsec to 15/30 nsec.
A
8
7
6
5
+24V
C 85
C 76
+5V
0.001uF
2200uF
C 75
35V
220uF
10V
6
5
4
U 42
LM317T
3
2
+24V
+5V
VI
VO
R155
1K
1%
R156
2.49K
1%
4
3
2
16-SEP-97
UPDATED PER ECN 86088.
ENCAD, Incorporated
6059 Cornerstone Court West
San Diego, CA 92121-3734
Title
Enhanced Main Board
(205325.sch)
Size
Document Number
B
205325
Date:
Monday, November 04, 2002
3
2
1
D
C
B
F
A
R e v
F
Sheet
1
o f
9
1
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