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Section 7: Command reference
Bit
Value
B0
Not used
B1
status.operation.instrument.smuX.trigger_overrun.ARM
B2
status.operation.instrument.smuX.trigger_overrun.SRC
B3
status.operation.instrument.smuX.trigger_overrun.MEAS
B4
status.operation.instrument.smuX.trigger_overrun.ENDP
B5-B15
Not used
As an example, to set bit B1 of the operation status SMU A trigger overrun enable register, set
status.operation.instrument.smua.trigger_overrun.enable =
status.operation.instrument.smua.trigger_overrun.ARM.
In addition to the above constants, operationRegister can be set to the numeric equivalent of the bit to set.
To set more than one bit of the register, set operationRegister to the sum of their decimal weights. For
example, to set bits B1 and B4, set operationRegister to 18 (which is the sum of 2 + 16).
Bit
Binary value
Decimal
Weights
Bit
Binary value
Decimal
Weights
Example
status.operation.instrument.smua.trigger_overrun.enable =
status.operation.instrument.smua.trigger_overrun.ARM
Also see
Operation Status Registers
status.operation.instrument.smuX.*
7-282
Model 2651A High Power System SourceMeter® Instrument Reference Manual
B7
B6
B5
0/1
0/1
0/1
128
64
32
7
6
5
(2
)
(2
)
(2
)
B15
B14
B13
0/1
0/1
0/1
32,768
16,384
8,192
15
14
13
(2
)
(2
)
(2
)
(on page E-20)
(on page 7-279)
B4
B3
B2
0/1
0/1
0/1
16
8
4
4
3
2
(2
)
(2
)
(2
)
B12
B11
B10
0/1
0/1
0/1
4,096
2,048
1024
12
11
10
(2
)
(2
)
(2
)
2651A-901-01 Rev. A / March 2011
Description
Not applicable.
Set bit indicates that the
arm event detector of the
SMU was already in the
detected state when a
trigger was received.
Bit B1 decimal value: 2
Set bit indicates that the
source event detector of
the SMU was already in
the detected state when a
trigger was received.
Bit B2 decimal value: 4
Set bit indicates that the
measure event detector of
the SMU was already in
the detected state when a
trigger was received.
Bit B3 decimal value: 8
Set bit indicates that the
end pulse event detector of
the SMU was already in
the detected state when a
trigger was received.
Bit B4 decimal value: 16
Not applicable.
B1
B0
0/1
0/1
2
1
1
0
(2
)
(2
)
B9
B8
0/1
0/1
512
256
9
8
(2
)
(2
)
Sets the ARM bit of the
operation status SMU A
trigger overrun enable
register using a
constant.
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