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Model 2651A High Power System SourceMeter® Instrument Reference Manual
status.operation.instrument.smuX.*
This attribute contains the operation status SMU X summary register set.
Type
TSP-Link accessible
Attribute
- -
.condition (R)
Yes
.enable (RW)
Yes
.event (R)
Yes
.ntr (RW)
Yes
.ptr (RW)
Yes
Usage
operationRegister = status.operation.instrument.smuX.condition
operationRegister = status.operation.instrument.smuX.enable
operationRegister = status.operation.instrument.smuX.event
operationRegister = status.operation.instrument.smuX.ntr
operationRegister = status.operation.instrument.smuX.ptr
status.operation.instrument.smuX.enable = operationRegister
status.operation.instrument.smuX.ntr = operationRegister
status.operation.instrument.smuX.ptr = operationRegister
operationRegister
X
Details
These attributes are used to read or write to the operation status SMU X summary registers. Reading a status
register returns a value. The binary equivalent of the returned value indicates which register bits are set. The
least significant bit of the binary number is Bit B0, and the most significant bit is Bit B15.The binary equivalent of
the value indicates which register bits are set. In the binary equivalent, the least significant bit is bit B0, and the
most significant bit is bit B15. For example, if a value of 1.02500e+02 (which is 1025) is read as the value of the
condition register, the binary equivalent is 0000 0100 0000 0010. This value indicates that bit B0 and bit B10 are
set.
B15
B14
**
>
0
0
* Least significant bit
** Most significant bit
For information about .condition, .enable, .event, .ntr, and .ptr registers, refer to
2) and
Enable and transition registers
meanings:
2651A-901-01 Rev. A / March 2011
Affected by
- -
Not applicable
Status reset
Status reset
Status reset
Status reset
The operation status SMU X summary register's status. A zero (0) indicates no bits
set (also send 0 to clear all bits); other values indicate various bit settings
Source-measure unit (SMU) channel (for example
status.operation.instrument.smua.enable applies to SMU channel A)
B13
B12
B11
B10
>
>
>
>
0
0
0
1
(on page E-18). The individual bits of this register have the following
Where saved
- -
Not saved
Not saved
Not saved
Not saved
Not saved
B9
B8
B7
B6
>
>
>
>
0
0
0
0
Section 7: Command reference
Default value
- -
Not applicable
0
0
0
1049 (All bits set)
B5
B4
B3
B2
>
>
>
>
0
0
0
0
Status register sets
B1
B0
>
*
1
0
(on page E-
7-279
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