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CHAPTER 12 INTERRUPT CONTROLLER
Sample interrupt routine
(1), (5) Increment PDRR.
(2), (6) Clear the interrupt source.
(3), (7) Decrement PDRR.
(4), (8) RETI
In this example, an interrupt with a higher priority occurs while interrupt routine I is running. This
example also prevents a hold request from being issued accidentally by incrementing the PDRR
at the beginning of each interrupt routine and decrementing the PDRR at the end.
Note:
•
Increment the PDRR at the beginning of the interrupt routine that is processed while DMA
transfer is performed (the CPU is held), and decrement it at the end of the interrupt routine.
Otherwise, DMA transfer is performed again while the interrupt routine is being executed.
•
In addition, do not increment and decrement the PDRR in a normal routine. This degrades
performance because DMA transfer cannot be performed while the interrupt routine is being
executed.
•
Exercise caution when setting interrupt levels in the HRCL register and in the ICR.
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