Fujitsu MB91150 Series Hardware Manual page 97

I Settings of the gear function
For the CPU clock control, the desired gear ratio can be set by setting the CCK1 and CCK0 bits
of the gear control register (GCR) to the desired values. For the peripheral clock control, the
desired gear ratio can be set by setting the PCK1 and PCK0 bits of that register to the desired
values.
[Example]
LDI:32 #GCR,R2
LDI:8
STB
LDI:8
STB
LDI:8
STB
LDI:8
STB
LDI:8
STB
When the CHC bit of the gear control register is set to 1, the output of the divided-by-2 circuit is
selected as the original clock. When it is set to 0, the same clock cycle as that from the
oscillation circuit is used.
To switch the original clock, the change with respect to the CPU and peripheral system is made
at the same time.
[Example]
LDI:8
LDI:32 #GCR,R2
STB
LDI:8
STB
LDI:8
STB
Figure 3.11-7 "Timing for gear switching" shows the timing for gear switching.
Original clock
CPU clock (a)
CPU clock (b)
Peripheral clock (a)
Peripheral clock (b)
CHC
CCK value
PCK value
#11111100b,R1 ; CCK=11,PCK=11,CHC=0
R1,@R2 ; CPU clock=1/8f, Periferal clock=1/8f,
f=direct
#01111000b,R1 ; CCK=01,PCK=10,CHC=0
R1,@R2 ; CPU clock=1/2f, Periferal clock=1/4f,
f=direct
#00111000b,R1 ; CCK=00,PCK=10,CHC=0
R1,@R2 ; CPU clock=f, Periferal clock=1/4f, f=direct
#00110000b,R1 ; CCK=00,PCK=00,CHC=0
R1,@R2 ; CPU clock=f, Periferal clock=f, f=direct
#10110000b,R1 ; CCK=10,PCK=00,CHC=0
R1,@R2 ; CPU clock=1/4f, Periferal clock=f, f=direct
#01110001b,R1 ; CCK=01,PCK=00,CHC=1
R1,@R2 ; CPU clock=1/2f, Periferal clock=f, f=1/2xtal
#00110001b,R1 ; CCK=00,PCK=00,CHC=1
R1,@R2 ; CPU clock=f, Periferal clock=f, f=1/2xtal
#00110000b,R1 ; CCK=00,PCK=00,CHC=0
R1,@R2 ; CPU clock=f, Periferal clock=f, f=direct
Figure 3.11-7 Timing for gear switching
01
00
CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT
00
81