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CHAPTER 17 DMA CONTROLLER
❍ Request pin input mode: Edge, Descriptor address: External
CLK
DREQn
Addr pin
Data pin
RD
WRn
DACK
DEOP
❍ Request input mode: Edge, Descriptor address: Internal
CLK
DREQn
Addr pin
Data pin
RD
WRn
DACK
DEOP
Note:
For the part from DREQn generation to the start of DMAC operation, only the conditions for
the fastest case are covered. The actual start of the DMAC operation may be delayed owing
to bus contention originating in CPU instruction fetching and data access.
386
#0H
#0L
#1H
#0H
#0L
(A)
S
S
#1L
#2H
#1H
#1L
#2H
(A)
#2L
S
#2L
S
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