Fujitsu MB91150 Series Hardware Manual page 202

CHAPTER 6 8/16-BIT UP/DOWN COUNTER/TIMER
I Count direction flag
The count direction flag (UDF1 and UDF0) indicates at the time of up/down counting whether
the counting operation preceding the current operation was counting up or down. Based on the
counter clock signal from the input of the AIN and BIN pins, this value of this flag changes for
each count. By checking this flag, the current rotation angle can be determined.
Table 6.6-2 "Count direction flag" summarizes how the count direction flag works.
Table 6.6-2 Count direction flag
UDF1, UDF0
01
10
11
I Count direction change flag
The CDCF is set when the counting direction changes between up and down. Simultaneously to
setting this flag, an interrupt request to the CPU can be generated. By referencing the interrupt
and count direction flag, the direction to which counting is changed can be determined.
However, note that when the period of direction change is short and multiple direction changes
are performed in succession, the direction that the flag indicates after the direction change may
return to the original direction so that it appears as if the counting direction has not changed at
all in between.
Table 6.6-3 "Count direction change flag" summarizes how the count direction change flag
works.
Table 6.6-3 Count direction change flag
CDCF
0
1
I Compare detection flag
The CMPF is set when the values of UDCR and RCR match during counting. This flag is set for
a match during counting up, match by occurrence of a reloading event, as well as when the
values already match when counting started.
However, a match during counting down (other than a match by compare during reload due to
an underflow) is not regarded as a match, and this flag is not set.
I Operations for 8 bits x 2 channels and 16 bits x 1 channel
This module can be used as an 8-bit up/down counter for two channels or a 16-bit up/down
counter for one channel. Setting the M16E bit of the CCRH0 register to 0 sets 8 bit mode for two
channels. Setting the bit to 1 sets 16 bit mode for one channel.
For operation in 16 bit mode for one channel, the registers CSR0, CCRL0, CCRH0 are valid and
the CSR1, CCRL1, and CCRH1 registers are invalid. In addition, the AIN0, BIN0, ZIN0 pins are
enabled as input pins, while the AIN1, BIN1, and ZIN1 pins are disabled.
186
Down count
B
Up count
B
Up/down occurs simultaneously (no counting operation is performed).
B
No direction change
Counting direction has changed (at least once).
Count direction
Count direction detection