Table of Contents
Advertisement
APPENDIX
Table A-1 I/O map (Continued)
Address
+0
000434
H
|
00047C
H
RSRR/WTCR [R, W]
000480
H
1-XXX-00
GCR [R/W, R]
000484
H
110011-1
PCTR [R/W]
000488
H
00XX0XXX
00048C
H
|
0005FC
H
DDR3 [W]
000600
H
00000000
000604
-
H
000608
-
H
00060C
H
00000000 00000001
000610
H
00000000 00000010
000614
H
00000000 00000011
000618
H
00000000 00000100
00061C
H
00000000 00000101
AMD0 [R/W]
000620
H
---00111
AMD5 [R/W]
000624
H
0--00000
000628
H
00062C
H
000630
-
H
446
Register
+1
STCR [R/W, W]
000111--
WPR [W]
XXXXXXXX
DDR2 [W]
00000000
DDR6 [W]
00000000
-
ASR1
[W]
ASR2
[W]
ASR3
[W]
ASR4
[W]
ASR5
[W]
AMD1 [R/W]
0--00000
EPCR0
[W]
----1100 -1111111
PCR6 [R/W]
00000000
+2
-
PDRR [R/W]
----0000
-
-
-
-
DDR5 [W]
00000000
-
AMR1
00000000 00000000
AMR2
00000000 00000000
AMR3
00000000 00000000
AMR4
00000000 00000000
AMR5
00000000 00000000
AMD32 [R/W]
00000000
-
EPCR1
-------- 11111111
-
-
Block
+3
Reserved
CTBR [W]
XXXXXXXX
Clock control
unit
PLL control
Reserved
-
DDR4 [W]
Data direction
00000000
register
DDR8 [W]
-0000000
[W]
[W]
[W]
[W]
T-unit
[W]
AMD4 [R/W]
0--00000
[W]
Reserved
Pull-up control
Advertisement
Table of Contents
