Fujitsu MB91150 Series Hardware Manual page 488

32-bit microcontroller
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APPENDIX
I Logical operation instructions
Table E-5 Logical operation instructions
Mnemonic
Type
AND Rj, Ri
AND Rj, @Ri
ANDH Rj, @Ri
ANDB Rj, @Ri
OR
Rj, Ri
OR
Rj, @Ri
ORH Rj, @Ri
ORB Rj, @Ri
EOR
Rj, Ri
EOR
Rj, @Ri
EORH Rj, @Ri
EORB Rj, @Ri
472
OP
CYCLE
A
82
1
A
84
1+2a
A
85
1+2a
A
86
1+2a
A
92
1
A
94
1+2a
A
95
1+2a
A
96
1+2a
A
9A
1
A
9C
1+2a
A
9D
1+2a
A
9E
1+2a
NZVC
Operation
CC--
Ri &= Rj
CC--
(Ri) &= Rj
CC--
(Ri) &= Rj
CC--
(Ri) &= Rj
CC--
Ri |= Rj
CC--
(Ri) |= Rj
CC--
(Ri) |= Rj
CC--
(Ri) |= Rj
CC--
Ri ^= Rj
CC--
(Ri) ^= Rj
CC--
(Ri) ^= Rj
CC--
(Ri) ^= Rj
Remarks
Word
Word
Half word
Byte
Word
Word
Half word
Byte
Word
Word
Half word
Byte

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