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- Although these bits can be read and written, these bits can only be set to 0.
- Read/modify/write instructions always return a reading value of 1.
[Bits 29, 25, 21, 17, 13, 9, 5, and 1] DIEn (DMA interrupt enable)
Specify whether to generate an interrupt at the end of DMA transfer over channel n (when
DEDn is set to 1).
0: Disables interrupts.
1: Enables interrupts.
- Upon reset, the bits in the register are initialized to 0.
- These bits can be read and written.
[Bits 28, 24, 20, 16, 12, 8, 4, and 0] DOEn (DMA operation enable)
Enables DMA transfer operation over channel n.
0: Disables operation.
1: Enables operation.
- Upon completion of DMA transfer over the appropriate channel (when DEDn is set to 1),
DOEn is reset to 0.
- If a clearing operation following completion of transfer, and a setting operation by loading
from a bus are performed concurrently, the setting operation has priority.
- Upon reset, the bits in the register are initialized to 0.
- These bits can be read and written.
CHAPTER 17 DMA CONTROLLER
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