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I Shift instructions
Table E-8 Shift instructions
Mnemonic
LSL Rj, Ri
*LSL # u5, Ri (u5:0 to 31)
LSL #u4, Ri
LSL2 #u4, Ri
LSR Rj, Ri
*LSR # u5, Ri (u5:0 to 31)
LSR #u4, Ri
LSR2 #u4, Ri
ASR Rj, Ri
*ASR # u5, Ri (u5:0 to 31)
ASR #u4, Ri
ASR2 #u4, Ri
I Immediate value set, 16-bit immediate value, and 32-bit immediate value transfer instructions
Table E-9 Immediate value set, 16-bit immediate value, and 32-bit immediate value transfer instructions
Mnemonic
LDI:32 #i32, Ri
LDI:20 #i20, Ri
LDI:8 #i8, Ri
*1
*LDI # {i8|i20|i32}, Ri
*1: If an immediate value is an absolute value, the assembler automatically selects i8, i20, or i32.
If the immediate value contains a relative value or external reference symbol, i32 is selected.
Type
OP
CYCLE
A
B6
1
C'
B4
1
C
B4
1
C
B5
1
A
B2
1
C'
B0
1
C
B0
1
C
B1
1
A
BA
1
C'
B8
1
C
B8
1
C
B9
1
Type
OP
CYCLE
E
9F-8
3
C
9B
2
B
C0
1
APPENDIX E Instruction Lists
NZVC
Operation
CC-C
Ri << Rj --> Ri
CC-C
Ri << u5 --> Ri
CC-C
Ri << u4 --> Ri
CC-C
Ri <<(u4+16) --> Ri
CC-C
Ri << Rj --> Ri
CC-C
Ri << u5 --> Ri
CC-C
Ri << u4 --> Ri
CC-C
Ri <<(u4+16) --> Ri
CC-C
Ri << Rj --> Ri
CC-C
Ri << u5 --> Ri
CC-C
Ri << u4 --> Ri
CC-C
Ri <<(u4+16) --> Ri
NZVC
Operation
----
i32 --> Ri
----
i20 --> Ri
----
i8 --> Ri
{i8|i20|i32} --> Ri
Remarks
Logical shift
Logical shift
Arithmetic shift
Remarks
The higher 12 bits are
zero-extended.
The higher 24 bits are
zero-extended.
475
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