Fujitsu MB91150 Series Hardware Manual page 55

[Bit 3] Negative flag
Indicates the sign when the arithmetic operation result is assumed to be an integer
represented in twos-complement form.
Value
0 Indicates that the result of an arithmetic operation was a positive value.
1 Indicates that the result of an arithmetic operation was a negative value.
The initial value after resetting is undefined.
[Bit 2] Zero flag
Indicates whether the result of an arithmetic operation is 0.
Value
0 Indicates that the result of an arithmetic operation is not 0.
1 Indicates that the result of an arithmetic operation is 0.
The initial value after resetting is undefined.
[Bit 1] Overflow flag
Indicates whether an overflow occurred as a result of an arithmetic operation, assuming that
the operand for the arithmetic operation is represented in twos-complement form.
Value
0 Indicates that no overflow occurred as the result of an arithmetic operation.
1 Indicates that an overflow occurred as the result of an arithmetic operation.
The initial value after resetting is undefined.
[Bit 0] Carry flag
Indicates whether a carry or borrow from the highest bit occurred during operation.
Value
0 Indicates that neither a carry nor borrow occurred.
1 Indicates that a carry or borrow occurred.
The initial value after resetting is undefined.
❍ System condition code register (SCR)
The system condition code register (SCR) is configured as follows:
CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT
[Initial value]
10 9 8
D1 D0 XX0
SCR
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