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FLCR and the 16-bit free run timer share the interrupt sources shown in the table below.
Interrupt source
16-bit free run timer/
flash
[Bit 5]: WE (Write enable)
Bit 5 is used to control writing of data or commands to the flash memory in CPU mode.
When this bit is 0, all data/command writing to the flash memory is disabled and the speed at
which data is read from the flash memory is doubled (32-bit access) compared to when this
bit is 1.
When this bit is 1, writing of data/commands to flash memory is enabled, making it possible
to start automatic algorithm. However, the speed at which data is read from the flash
memory is slower (16-bit access) compared to when this bit is 0.
Be sure to verify that the automatic algorithm (e.g., write and erase) is stopped in
accordance with the RDY bit before rewriting the value of this bit. When the RDY bit is 0, the
value of this bit cannot be rewritten.
In flash memory mode, writing is enabled regardless of the status of this bit.
Writing to flash memory is disabled and the speed at which data is read from
0
the flash memory is twice that as when this bit is 1.
Writing the flash memory is enabled and the speed at which data is read from
1
the flash memory is slower than when this bit is 0.
•
At reset, this bit is initialized to 0.
•
This bit can both be read and written.
[Bit 4]: RDY (Ready)
Bit 4 is used to indicate the operating status of the automatic algorithm (e.g., write and
erase).
When this bit is 0, new data cannot be written and the Erase command is not accepted
because data is being written or erased by the automatic algorithm. Also, data cannot be
read from the flash memory addresses.
The read data indicates the flash memory status.
Data cannot be read and Write and Erase commands are not accepted while
0
data is being written or erased.
1
Data can be read and Write and Erase commands can be accepted.
•
At reset, this bit is not initialized (processing of this bit conforms to the status of the flash
memory at that point of time).
•
This is a read-only bit. Write operations do not affect the value of this bit.
[Bits 3, 2, and 1]: Reserved bits
In write operations, be sure to set these bits to 0.
Interrupt No.
In decimal
In hexadecimal
notation
notation
62
3E
CHAPTER 21 FLASH MEMORY
Interrupt
TBR default
Offset
level
address
ICR46
304
000FFF04
H
H
419
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