Basic Read Cycle - Fujitsu MB91150 Series Hardware Manual

CHAPTER 4 BUS INTERFACE
4.5.1

Basic Read Cycle

This section describes the operations of the basic read cycle.
I Basic read cycle timing chart
Figure 4.5-1 "Timing chart of the basic read cycle" shows an example of basic read cycle timing
under the following conditions:
• Bus width: 16 bits
• Access type: in words
• Access to CS0 area
Note:
This model does not use CS4 and CS5 outputs.
[Operation]
• The CLK outputs the pulses for the operating clock of the external bus. If the clock doubler is
off, the operating clocks of the CPU and that of the external bus are in 1:1 relationship and
the clock pulses output from the CLK have the same frequency as the clock pulses of the
CPU. If the clock doubler is on, the operating clocks of the CPU and that of the external bus
are in 1:1/2 relationship and the clock pulses output from the CLK have a frequency that is
half that of the CPU clock pulses.
132
Figure 4.5-1 Timing chart of the basic read cycle
BA1
CLK
A23-00 #0
D31-24
D23-16
RD
WR0
WR1
(CS0)
(CS1)
(CS2)
(CS3)
(DACK0)
(DEOP0)
Access to the
higher halfword
of an address
Notes:
The sharp-symbol (#) of A23-A00 indicates the lower two bits of
an address.
The sharp-symbol (#) of D31 to D16 indicates the byte address
for read data.
(DACK0) and (DEOP0) indicate DMAC bus cycles.
The arrow-symbol ( ) indicates the timing of fetching read data.
BA2 BA1 BA2
#2
#0 #2
#1 #3
Access to the
lower halfword
of an address
If the gear is set, the CLK frequency is decreased