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CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT
I Block diagram of the clock generator
Figure 3.11-2 "Block diagram of the clock generator" shows the block diagram of the clock
generator.
Oscil-
X 0
lation
X 1
circuit
Internal interrupt
Internal reset
DMA request
Power-on detection circuit
V
CC
R
G N D
RST pin
68
Figure 3.11-2 Block diagram of the clock generator
[Gear control block]
GCR register
1 / 2
P L L
[Stop and sleep control block]
STCR register
PDRR register
[Reset source circuit]
RSRR register
[Watchdog control block]
WPR register
CTBR register
CPU gear
Peripheral
gear
Internal clock
generation
circuit
Status
transition
control circuit
Reset
generation
F/F
Watchdog F/F
Count clock
Time-base timer
CPU Clock
Internal bus clock
Internal peripheral clock
STOP status
SLEEP status
CPU hold request
Internal reset
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